Flip-Flops problems
- 1. If an input is activated by a signal transition, it is ________.
Options- A. edge-triggered
- B. toggle triggered
- C. clock triggered
- D. noise triggered Discuss
Correct Answer: edge-triggered
- 2. Which of the following is correct for a gated D flip-flop?
Options- A. The output toggles if one of the inputs is held HIGH.
- B. Only one of the inputs can be HIGH at a time.
- C. The output complement follows the input when enabled.
- D. Q output follows the input D when the enable is HIGH. Discuss
Correct Answer: Q output follows the input D when the enable is HIGH.
- 3. What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output. Discuss
Correct Answer: It has an invalid state.
- 4. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
Options- A. The power supply is probably noisy.
- B. The switch contacts are bouncing.
- C. The socket contacts on the register IC are corroded.
- D. The register IC is intermittent and failure is imminent. Discuss
Correct Answer: The switch contacts are bouncing.
- 5. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
Options- A. clock is LOW
- B. slave is transferring
- C. flip-flop is reset
- D. clock is HIGH Discuss
Correct Answer: clock is HIGH
- 6. The output of a gated S-R flip-flop changes only if the:
Options- A. flip-flop is set
- B. control input data has changed
- C. flip-flop is reset
- D. input data has no change Discuss
Correct Answer: control input data has changed
- 7. The toggle condition in a master-slave J-K flip-flop means that Q and
will switch to their ________ state(s) at the ________.
Options- A. opposite, active clock edge
- B. inverted, positive clock edge
- C. quiescent, negative clock edge
- D. reset, synchronous clock edge Discuss
Correct Answer: opposite, active clock edge
- 8. Which is not an Altera primitive port identifier?
Options- A. clk
- B. ena
- C. clr
- D. prn Discuss
Correct Answer: clr
- 9. Connecting components together using HDL is not difficult.
Options- A. True
- B. False Discuss
Correct Answer: True
- 10. VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.
Options- A. True
- B. False Discuss
Correct Answer: True
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