Flip-Flops Questions

• What is the significance of the J and K terminals on the J-K flip-flop?
• If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
• How is a J-K flip-flop made to toggle?
• Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
• How many flip-flops are required to produce a divide-by-128 device?
• A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
• For an S-R flip-flop to be set or reset, the respective input must be:
• A 555 operating as a monostable multivibrator has an R1 of 220 kΩ. Determine C1 for a pulse width of 4 ms.
• Which is not a real advantage of HDL?
• A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
• A 555 operating as a monostable multivibrator has an R1 of 1 MΩ. Determine C1 for a pulse width of 2 s.
• Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
• If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
• Which of the following is not generally associated with flip-flops?
• Edge-triggered flip-flops must have:
• A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
• An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
• The pulse width of a one-shot circuit is determined by ________.
• Which of the following is correct for a D latch?
• Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.