VHDL component instantiation syntax In VHDL, each instance of a component is addressed (labeled) using what syntactic form?

Introduction / Context:
Structural VHDL connects components by instantiating them with labels. The label uniquely identifies each instance in the design hierarchy for simulation, debugging, and synthesis reports.

Given Data / Assumptions:

• VHDL syntax relies on a label (instance name) and a component/entity name.
• The general form is followed by a port map association list.
• Tools reference instances by their labels in messages and waveforms.

Concept / Approach:
The canonical instantiation form is: label : entity work.entity_name port map (...); or, when using components: label : component_name port map (...); The crucial part is the label followed by a colon, then the referenced entity/component identifier.

Step-by-Step Solution:

Verification / Alternative check:
Any VHDL reference manual shows examples using the label-colon-component form. Vendor templates in IDEs auto-generate this structure.

Why Other Options Are Wrong:

• Semicolon after the name: Semicolons terminate statements, not label association.
• Following with the library name or a library number: Libraries are referenced in the entity path; they do not replace the label:component form.

Common Pitfalls:
Confusing component instantiation (component/label) with direct entity instantiation (entity work.X), or omitting the label, which reduces readability and hierarchical traceability.

Final Answer:
A name followed by a colon and the name of the library primitive