Cross-coupled NOR latch polarity For a cross-coupled NOR flip-flop (latch), are the set and reset control inputs active-HIGH or active-LOW?
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Aactive-HIGH
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Bactive-LOW
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Cboth (depends on output polarity only)
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Dneither (they are level-insensitive)
Answer
Correct Answer: active-HIGH
Explanation
Introduction / Context:Cross-coupled latches can be realized with either NOR or NAND gates. Their input polarities differ: understanding which version uses active-HIGH versus active-LOW controls is essential for interfacing with the rest of a digital system.
Given Data / Assumptions:
- Device: cross-coupled NOR latch.
- Inputs: S (set) and R (reset) applied to NOR gate inputs.
- Outputs: Q and Q̄ taken from the gates’ outputs in the standard configuration.
Concept / Approach:A NOR gate outputs HIGH only when all inputs are LOW. Therefore, applying a HIGH on one input forces that NOR output LOW, which—through cross-coupling—drives the opposite output HIGH. Thus, asserting a HIGH on S sets Q=1; asserting a HIGH on R resets Q=0. Hence the NOR latch uses active-HIGH set and reset inputs.
Step-by-Step Solution:
Apply S=1, R=0: Left NOR output goes 0; right NOR sees 0 on its feedback input and holds 1 → Q=1 (set).Apply R=1, S=0: Right NOR output goes 0; left NOR rises to 1 → Q=0 (reset).With S=0 and R=0: Both NORs are governed by feedback, retaining the last state (hold).With S=1 and R=1: Both outputs forced LOW (invalid/forbidden for the SR latch), leading to metastability upon release.Verification / Alternative check:Compare with the NAND latch: it uses active-LOW controls (asserting a LOW performs the action). The two are duals with inverted input polarities.
Why Other Options Are Wrong:
- active-LOW: That describes the NAND-based latch, not NOR-based.
- Both / neither: Input polarity is well-defined; the latch is level-sensitive to explicit HIGH assertions for control.
Common Pitfalls:Mixing up NOR and NAND latch conventions, or assuming output inversion changes input active level (it does not).
Final Answer:active-HIGH