Flip-Flops Questions

• A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.
• All multivibrators require feedback.
• Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.
• The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.
• VHDL does require a special designation for an output with a feedback.
• Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.
• Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.
• The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.
• A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.
• Pulse-triggered or level-triggered devices are the same.
• A latch can act as a contact-bounce eliminator.
• A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.
• When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.
• In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.
• PRESET and CLEAR inputs are normally synchronous.
• Edge-triggered flip-flops can be identified by the triangle on the clock input.
• A J-K flip-flop and associated waveforms are shown below. The circuit is operating properly.
• A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.
• A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.
• Latches are tristate devices whose state normally depends on asynchronous inputs.