Flip-Flops Questions

• On a J-K flip-flop, when is the flip-flop in a hold condition?
• A positive edge-triggered D flip-flop will store a 1 when ________.
• A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
• When is a flip-flop said to be transparent?
• In VHDL, in which declaration section is a COMPONENT declared?
• Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
• The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
• In VHDL, how many inputs will a primitive JK flip-flop have?
• One example of the use of an S-R flip-flop is as a(n):
• Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
• If an input is activated by a signal transition, it is ________.
• Which of the following is correct for a gated D flip-flop?
• What is one disadvantage of an S-R flip-flop?
• A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
• A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
• The output of a gated S-R flip-flop changes only if the:
• The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
• Which is not an Altera primitive port identifier?
• Connecting components together using HDL is not difficult.
• VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.