Diagnosing a JK flip-flop with asynchronous controls A circuit fails to function. Logic probe readings show CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q is HIGH. PRE is LOW. (CLR is not asserted.) Which condition best explains the fault?

Introduction / Context:
JK flip-flops commonly include asynchronous preset (PRE) and clear (CLR) inputs, often active-LOW. When asserted, these override synchronous J, K, and CLK activity. Correctly interpreting probe indications is essential for debugging nonresponsive sequential circuits.

Given Data / Assumptions:

• J and K inputs are pulsing (valid activity).
• CLK is pulsing (clock present).
• Q output is stuck HIGH.
• PRE line reads LOW; asynchronous controls are active-LOW on most TTL/CMOS JK devices.

Concept / Approach:
If PRE is active-LOW and held LOW, the flip-flop is asynchronously forced to Q=1 regardless of J, K, or clock. As long as PRE remains asserted, no synchronous toggling can change the state, which explains a constant HIGH Q amidst active inputs and clock.

Step-by-Step Solution:

Verification / Alternative check:
Temporarily release PRE (drive it HIGH via pull-up). If the device then responds to clock and J/K, the diagnosis is confirmed. Checking CLR should show it inactive (HIGH) to avoid forcing reset.

Why Other Options Are Wrong:

• No problem: Contradicted by lack of state changes at Q with active J/K/CLK.
• Clock should be held HIGH: Holding CLK HIGH would disable edge/level sampling, not fix a stuck state.
• CLR stuck HIGH: On active-LOW CLR, HIGH is the inactive state, so this would not force Q HIGH.

Common Pitfalls:
Forgetting that PRE/CLR are usually active-LOW, or assuming synchronous inputs can override asynchronous controls (they cannot).

Final Answer:
The PRE is stuck LOW.