Flip-Flops Questions

• The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.
• A gated S-R flip-flop goes into the CLEAR condition when ________.
• The signal used to identify edge-triggered flip-flops is ________.
• A gated D latch does not have ________.
• A positive edge-triggered flip-flop will accept inputs only when the clock ________.
• A gated S-R flip-flop is in the hold condition whenever ________.
• The postponed symbol () on the output of a flip-flop identifies it as being ________.
• When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.
• The advantage of a J-K flip-flop over an S-R FF is that ________.
• A major drawback to an latch is its ________.
• The action of ________ a FF or latch is also called resetting.
• The ________ is the time interval immediately following the active transition of the clock signal.
• The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.
• Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
• The term hold always means ________.
• The asynchronous inputs on a J-K flip-flop ________.
• A flip-flop operation is described as a toggle when the result after a clock is ________.
• The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.
• When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.
• The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.