SR latch polarity (NAND version) In a cross-coupled NAND flip-flop (latch), the set and reset inputs are normally active-LOW. How can we modify the circuit so that it instead has active-HIGH S and R control inputs (i.e., asserting a HIGH performs set/reset)?

Difficulty: Easy

Correct Answer: Invert the S-R inputs.

Explanation:


Introduction / Context:
NAND- and NOR-based cross-coupled latches implement the same memory function but with different input polarities. A standard NAND latch uses active-LOW S and R (bringing an input LOW asserts that function). Many systems, however, specify active-HIGH control signals. This question asks how to reconcile that by simple logic-level adaptation.


Given Data / Assumptions:

  • Device: cross-coupled NAND SR latch.
  • Default polarity: S and R are active-LOW.
  • Goal: make S and R active-HIGH without changing the fundamental latch core.


Concept / Approach:
Polarity conversion is achieved by inversion. If a function is active-LOW and we require active-HIGH behavior, we place an inverter in series with each control line. A HIGH at the external interface becomes a LOW into the NAND input, thus producing the original active-LOW action inside the latch while presenting an active-HIGH interface externally.


Step-by-Step Solution:

Identify the present polarity: S_activeLOW and R_activeLOW into a NAND latch.Insert one inverter on S and one on R (or use NAND gates wired as inverters).Now external S_high → inverter → internal S_low (asserts set). External R_high → inverter → internal R_low (asserts reset).Outputs Q and Q̄ are unchanged; only control polarity is adapted.


Verification / Alternative check:
Truth-check one case: External S=1, R=0 should set Q. After inversion, internal S=0, R=1 into the original NAND latch, which indeed sets Q=1. All other cases map consistently.


Why Other Options Are Wrong:

  • It can't be done: Incorrect—simple inversion is standard practice.
  • Invert the Q outputs: Changes output polarity, not input control polarity.
  • Insert RC networks: Affects timing/edges, not logic-level polarity.


Common Pitfalls:
Confusing active-level conventions, or attempting to swap NAND for NOR (which changes internal behavior rather than simply inverting inputs).


Final Answer:
Invert the S-R inputs.

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