Latch behavior — why cross-coupled gates hold state NOR- and NAND-based latches tend to remain latched. Which configuration feature is responsible for this bistable memory action?

Introduction / Context:
Set–reset latches made from basic NOR or NAND gates are the simplest memory elements in digital electronics. Their ability to “remember” a previous input depends on mutual feedback between the gates, establishing two stable operating points. This question probes your understanding of the structural reason behind latch behavior.

Given Data / Assumptions:

• Two-gate latch constructed from NOR or NAND devices.
• Inputs briefly drive the latch to a desired state.
• The latch must maintain that state after the inputs are released.

Concept / Approach:
Cross coupling means the output of each gate feeds an input of the other, creating positive feedback. When one output is HIGH and the other LOW, the feedback reinforces this condition. A short set or reset pulse flips the pair into the alternative stable state, which is again self-reinforced after the pulse ends.

Step-by-Step Reasoning:

Verification / Alternative check:
Plot simple DC transfer characteristics or simulate the pair; you will observe two stable equilibrium points and one unstable transition point, illustrating classic bistability due to positive feedback through cross coupling.

Why Other Options Are Wrong:

• Gate impedance / low input voltages: not the fundamental cause of memory; latching results from topology, not absolute impedances.
• Asynchronous operation: describes timing discipline, not the physical mechanism of storage.
• Schmitt triggering: introduces hysteresis for clean switching but is not required for basic latching.

Common Pitfalls:

• Confusing the presence of feedback (cross coupling) with edge-triggering; edge-triggered flip-flops are built from latches but include additional gating.

Final Answer:
cross coupling