Flip-Flops Questions

• The term CLEAR always means that .
• Parallel data transfers between two different sets of registers require more than one shift pulse.
• The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.
• A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.
• A flip-flop is in the CLEAR condition when .
• The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
• A D latch has one data-input line.
• The 7474 has two distinct types of inputs: synchronous and asynchronous.
• The gated S-R flip-flop is asynchronous.
• Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.
• A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.
• Multivibrators must be level-triggered.
• Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.
• The 555 timer can be used in either the astable or monostable modes.
• The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
• The S-R flip-flop has no invalid or unused state.
• A one-shot circuit is also known as a timer.
• Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
• Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.
• When the output of the NOR gate S-R flip-flop is and , the inputs are .