Master–slave flip-flop timing In a master–slave flip-flop built from level-sensitive latches, during which clock (gate) level is the master latch enabled (transparent)?

Introduction / Context:
A master–slave flip-flop is formed by cascading two level latches with opposite clock polarity so that an overall edge-triggered behavior results. Understanding which level enables the master versus the slave is crucial to predict sampling and update times.

Given Data / Assumptions:

• Topology: master latch followed by slave latch.
• Clocking: complementary enabling—when master is open, slave is closed, and vice versa.
• Conventional positive-edge design: master is enabled when CLK = HIGH; slave is enabled when CLK = LOW.

Concept / Approach:
With a positive-edge master–slave, the master captures input while the clock is HIGH. At the transition to LOW, the master closes, the slave opens, and the captured state transfers to the output, producing an effective capture on the rising edge (HIGH-to-LOW handoff).

Step-by-Step Solution:

Verification / Alternative check:
Check a timing diagram: input changes during CLK=HIGH can affect master but do not reach Q until the subsequent LOW phase enables the slave, aligning observable update to the edge boundary.

Why Other Options Are Wrong:

• Gate LOW: That enables the slave in the standard positive-edge arrangement, not the master.
• Both / neither: Contradict the complementary nature of the two latches.

Common Pitfalls:
Assuming both latches enable on the same level (which would form a transparent path) or confusing positive- and negative-edge configurations.

Final Answer:
when the gate is HIGH