Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Flip-Flops
A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
The output is always low; the circuit is defective.
The Q output should be the complement of the output; the S and R terminals are reversed.
The Q should be following the R input; the R input is defective.
There is nothing wrong with the circuit.
Correct Answer:
The output is always low; the circuit is defective.
← Previous Question
Next Question→
More Questions from
Flip-Flops
A 555 operating as a monostable multivibrator has an R1 of 1 MΩ. Determine C1 for a pulse width of 2 s.
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Which of the following is not generally associated with flip-flops?
Edge-triggered flip-flops must have:
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
The pulse width of a one-shot circuit is determined by ________.
Which of the following is correct for a D latch?
Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments