Glitches when deriving two-phase clocks from a positive-edge J–K flip-flop A positive edge-triggered J–K flip-flop is used to create a two-phase clock, but oscilloscope inspection shows glitches. What causes the glitches, and how can the issue be corrected?

Introduction / Context:
Generating two-phase, nonoverlapping clocks from a single clock source often involves gating a clock with flip-flop outputs (e.g., Q and Q_bar). However, when gating occurs around the same edge that updates the flip-flop, small propagation delays can create brief hazards or glitches. Recognizing this race and choosing the correct mitigation is a practical design skill for clocking networks.

Given Data / Assumptions:

• Positive-edge-triggered J–K flip-flop produces complementary outputs Q and Q_bar.
• An AND gate (or similar gating) uses Q/Q_bar with the clock to form phases.
• Glitches are visible at transitions on a scope.

Concept / Approach:

At the same instant the clock edge arrives, the J–K flip-flop outputs transition after a finite propagation delay. If those outputs are used to gate the clock itself, the overlap between the changing outputs and the actively switching clock can transiently enable the gate, creating short pulses (glitches). Changing the triggering edge so outputs settle before the opposite edge arrives can break the race.

Step-by-Step Solution:

Verification / Alternative check:

Simulate timing with realistic delays: observe that with positive-edge gating and positive-edge update, narrow spikes occur. Switching to negative-edge flip-flop eliminates spikes because outputs change on the falling edge, away from the active gate edge.

Why Other Options Are Wrong:

Floating PRESET/CLEAR: can cause issues but not specifically edge-correlated glitches in two-phase generation.

Race between J and K inputs: with static J and K, the problem is not J/K but the interaction of clock and Q transitions.

Replacing AND with NAND: changes polarity but does not remove the timing race that causes the spikes.

Common Pitfalls:

Ignoring real propagation delays; assuming ideal, instantaneous flip-flop outputs; forgetting to provide nonoverlap or phase separation when deriving multiple phases from one clock.

Final Answer:

A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.