Understanding the D latch Which statement correctly describes the behavior of a level-enabled D latch?

Introduction / Context:
A D (data) latch is a level-sensitive storage element widely used for pipeline staging and simple registers. Its key characteristic is that, while enabled, the output tracks the input; when disabled, it holds the last sampled value. Distinguishing this behavior from edge-triggered flip-flops is crucial in timing design.

Given Data / Assumptions:

• Device: level-enabled D latch with an enable (EN) signal.
• Polarity: assume active-HIGH enable unless otherwise stated.
• Outputs: Q and Q̄ (complement) available in many implementations.

Concept / Approach:
When EN = 1 (HIGH), the latch is transparent, meaning Q reflects D in real time (within propagation delay). When EN = 0 (LOW), the latch is opaque, meaning Q retains its previous value regardless of changes on D. This distinguishes a latch from an edge-triggered flip-flop, which samples only on clock transitions.

Step-by-Step Solution:

Verification / Alternative check:
Examine a timing diagram: during EN = 1, any transition on D is mirrored at Q; during EN = 0, Q is flat despite D activity. Simulation waveforms confirm this relationship precisely.

Why Other Options Are Wrong:

• Output toggles if one input is held HIGH: Describes a T or JK flip-flop, not a D latch.
• Only one input can be HIGH: Not applicable; D latch has data and enable, not mutually exclusive inputs.
• Output complement follows the input: Q̄ follows NOT D when enabled, but Q follows D; the statement is misleading.

Common Pitfalls:
Confusing latch transparency with flip-flop edge-triggering, and forgetting that poor enable timing can pass hazards through the latch.

Final Answer:
Q output follows the input D when the enable is HIGH.