Negative-edge-triggered D flip-flop — concise functional description Which statement best describes a negative-edge-triggered D flip-flop's operation?

Introduction / Context:
D flip-flops are the primary data storage elements in synchronous systems. The triggering edge (positive or negative) dictates when the input is sampled. A negative-edge-triggered device captures the input as the clock transitions from HIGH to LOW, then holds that value until the next qualifying edge. Accurately articulating this behavior prevents timing mistakes in design and analysis.

Given Data / Assumptions:

• Flip-flop is negative-edge-triggered (active on NGT = negative-going transition).
• D is the data input; Q is the stored output.
• No asynchronous set/reset is active.

Concept / Approach:

At the instant of the falling clock edge, the flip-flop samples D and updates Q to that value, provided setup and hold times around the edge are satisfied. Between edges, changes on D do not affect Q. This one-edge sampling distinguishes flip-flops from level-sensitive latches, which are transparent for the duration of an enable/clock level.

Step-by-Step Solution:

Verification / Alternative check:

Examine a timing diagram: apply a changing D; only values present at the falling edges appear at Q one-for-one; asynchronous variations in between edges are ignored.

Why Other Options Are Wrong:

Q identical to CLK when D is HIGH: nonsense; Q follows D sampling, not the clock signal.

Q identical to D on PGT (positive-going transition): contradicts 'negative-edge-triggered.'

Q always identical to D: that describes a transparent latch, not an edge-triggered FF.

Common Pitfalls:

Violating setup/hold times leading to metastability; misinterpreting the edge sense; expecting Q to respond to D changes between edges.

Final Answer:

The logic level at the D input is transferred to Q on NGT of CLK.