Active-HIGH SR latch behavior An SR latch with active-HIGH inputs is driven with S = 1 and R = 0. In this condition, what state does the latch assume (indicate the state of Q)?

Introduction / Context:
An SR (Set–Reset) latch is the simplest bistable storage element in digital electronics. Understanding how input polarity (active-HIGH or active-LOW) affects the state transition is essential for correctly interfacing latches with combinational logic and for diagnosing behavior in larger sequential circuits.

Given Data / Assumptions:

• Latch type: SR latch with active-HIGH control inputs.
• Applied inputs: S = 1 (asserted), R = 0 (deasserted).
• Outputs: Q and Q̄, where Q̄ is the logical complement of Q under normal operation.

Concept / Approach:
With active-HIGH inputs, a logic HIGH on S commands the latch to store a 1 (set), while a logic HIGH on R commands the latch to store a 0 (reset). If both inputs are LOW, the latch holds its previous state. The combination S = 1 and R = 1 is generally considered invalid/forbidden for an SR latch because it attempts to force both outputs LOW (for NOR-based implementation) and can lead to metastability upon release.

Step-by-Step Solution:

Verification / Alternative check:
Consider a cross-coupled NOR implementation: S = 1 forces the left NOR output LOW, which releases the opposite side to go HIGH, producing Q = 1. Tracing the feedback confirms a stable set condition as long as R remains 0.

Why Other Options Are Wrong:

• Reset state: Requires R = 1 (asserted reset), which is not the case.
• Hold state: Occurs only when both S and R are deasserted (S = 0, R = 0).
• Invalid/forbidden state: Associated with S = 1 and R = 1, not with S = 1 and R = 0.

Common Pitfalls:
Confusing active-HIGH with active-LOW versions (for NAND-based latches, assertions are LOW), and assuming the hold condition applies whenever one input is 0 (it applies only when both are inactive).

Final Answer:
Set state (Q = 1, Q̄ = 0)