How to force toggling in a J–K flip-flop Under which input condition does a J–K flip-flop toggle its output state on each active clock edge?

Introduction / Context:
The J–K flip-flop extends the S–R flip-flop by defining a behavior for the case when both inputs are asserted. That special case enables toggling, making the J–K FF useful as a programmable T (toggle) flip-flop for counters and clock division. Mastering the input-state mapping is essential for designing sequential logic.

Given Data / Assumptions:

• Edge-triggered J–K FF sampled at the active clock edge.
• Inputs J and K can be 0 or 1 at the sampling moment.
• No asynchronous set or reset is active.

Concept / Approach:

The characteristic behavior is: J = 0, K = 0 → hold; J = 1, K = 0 → set; J = 0, K = 1 → reset; J = 1, K = 1 → toggle (Q_next = not Q_previous). Thus, to create a divide-by-2 output or a square wave, tie J and K high and clock the device.

Step-by-Step Solution:

Verification / Alternative check:

Build a small counter: with J = K = 1, Q changes state every clock edge; viewing on a scope confirms a 50% duty cycle at half the input frequency (ignoring setup/hold and propagation delays).

Why Other Options Are Wrong:

J = 0, K = 0: holds state.

J = 1, K = 0: sets.

J = 0, K = 1: resets.

Common Pitfalls:

Forgetting to meet setup/hold timing on J and K; enabling asynchronous clears that inhibit toggling; misunderstanding that toggling occurs only at the clock edge, not continuously.

Final Answer:

J = 1, K = 1