D flip-flop with positive-going transition (PGT) clock — action from CLEAR state A D flip-flop uses a PGT (positive-going transition) clock and is currently in the CLEAR state (Q = 0). Which input condition will cause the device to change state on the next clock event?

Introduction / Context:
D flip-flops sample the D input at the active clock edge and transfer it to Q. If the device is positive-edge (PGT) triggered, only a rising edge causes the state to update. Knowing which input combinations lead to a state change is key for designing registers and synchronous pipelines.

Given Data / Assumptions:

• Current state: CLEAR → Q = 0.
• Clock sensitivity: positive-going transition (PGT).
• No asynchronous set/clear asserted at the event.

Concept / Approach:
At the rising edge, Qnext becomes the present D. To change from Q = 0 to Q = 1, present D must be 1 at the moment of the PGT. Negative-going transitions (NGT) are irrelevant to a PGT device and produce no state change under normal operation.

Step-by-Step Reasoning:

Verification / Alternative check:
Simulate or consult timing diagrams: with D = 1 held stable for setup/hold around the rising edge, Q updates to 1 immediately after the edge; with D = 0, Q remains 0. Negative edges do not trigger in a PGT device.

Why Other Options Are Wrong:

• Any NGT option: does not trigger a PGT flip-flop.
• PGT with D = 0: samples 0 and keeps Q = 0 (no state change from CLEAR).

Common Pitfalls:

• Ignoring setup/hold requirements; even with D = 1, violating timing can prevent a reliable change.

Final Answer:
CLOCK PGT, D = 1