Q: Characteristics of an ideal memory device Which statement best describes an “ideal” memory for digital systems?

Introduction / Context:Designers dream of an “ideal” memory that combines the best traits of today’s RAM and nonvolatile technologies. Understanding these traits helps explain why systems mix multiple memory types (SRAM cache, DRAM main memory, Flash/EEPROM storage). Given Data / Assumptions: Ideal memory is a conceptual target, not a single existing device. Desirable traits include capacity, nonvolatility, and in-system read/write capability. No trade-offs for speed, endurance, or power are implied in the idealization. Concept / Approach: High capacity minimizes cost per bit. Nonvolatility preserves data without power. In-system read/write capability means byte or word programmability without special equipment, enabling firmware updates and general data storage under normal operating conditions. The ideal memory would combine all these benefits simultaneously. Step-by-Step Solution: List key attributes: capacity, nonvolatile retention, and easy read/write.Check options: A, B, and C are all desirable and none are mutually exclusive.Therefore, the ideal memory has all the above characteristics → option D. Verification / Alternative check: Real devices: DRAM offers capacity but is volatile; SRAM offers speed but low density; Flash/EEPROM offer nonvolatility and in-system programming but slower writes. The ideal merges these strengths. Why Other Options Are Wrong: Only capacity: ignores data loss on power removal. Only nonvolatility: ignores practical write needs. Only in-system R/W: without capacity and retention, it falls short. Common Pitfalls: Equating “ideal” with a single commercial part; actual devices involve trade-offs. Final Answer: has all of the above characteristics

Q: Reading logic symbols — output bubbles/triangles In the shown memory/logic device, small inverted triangles (inverters) appear at the outputs. What do they indicate about the outputs?

Introduction / Context:Schematic symbols use small shapes to communicate logic polarity. A tiny inversion symbol at a pin tells you whether the external “active” level is a logical LOW or HIGH. This is crucial when interfacing memory or logic outputs to downstream circuits and buses. Given Data / Assumptions: The symbol shows a small inversion marker (often a small triangle with a bubble, or a bubble) placed at the output pins. We are to infer the output's active polarity. No other special drive symbols (e.g., tri-state enable bars) are indicated. Concept / Approach: An inversion indicator denotes logical inversion between the internal node and the external pin. When placed on an output, it signals that the output is asserted at logical 0 (active-LOW). Datasheets often label such pins with a bar over the name (e.g., OE̅) or a trailing “#” or “/”. Step-by-Step Solution: Identify inversion indicator at the output.Outputs that are “active” when LOW are said to be active-LOW.Therefore, the inverters indicate active-LOW outputs. Verification / Alternative check: Cross-check with common logic symbols: input or output bubbles consistently mean active-LOW polarity; triangles alone can denote buffers or amplifiers but a bubble denotes inversion/active-LOW. Why Other Options Are Wrong: High fan-out claim is a drive strength attribute, not a symbol for inversion. “Change-detect” behavior is unrelated to inversion symbols. Tristate is typically shown with an enable pin (often active-LOW) and not merely with inversion at outputs. Common Pitfalls: Confusing tri-state capability with active-LOW polarity indicators. Final Answer: They represent inverters and mean that the outputs are active-LOW.

Question 1

Nonvolatile memories — UV-erasable category Which type of ROM device can be erased by exposure to ultraviolet (UV) light through a quartz window?

Accepted Answer

Introduction / Context:Read-only memory (ROM) technologies differ in how (and whether) they can be programmed and erased. Recognizing how each type is altered in the field is essential for hardware maintenance, embedded updates, and legacy system repair. Given Data / Assumptions: Mask ROM: contents fixed at manufacture; cannot be electrically or optically erased. EPROM: erasable programmable ROM with a quartz window; erased by UV light. EEPROM/Flash: electrically erasable, no UV window required. Concept / Approach:EPROMs use floating-gate transistors whose stored charge can be removed by high-energy UV photons. The chip package features a quartz window to allow UV light to reach the die. After erasure, the device can be reprogrammed with a PROM/EPROM programmer. Step-by-Step Solution:Identify which memories are field-erasable: EPROM, EEPROM/Flash.Determine which requires UV rather than electrical erase: EPROM.Therefore, the UV-erasable device is EPROM. Verification / Alternative check:EPROM packages (e.g., 27C256) have conspicuous windows labeled “Erase before programming” specifying UV wavelength and exposure times (often ~253.7 nm for several minutes). Why Other Options Are Wrong: ROM/Mask ROM: Not erasable in the field. EEPROM: Erased electrically, not by UV. Common Pitfalls: Confusing EPROM and EEPROM due to similar names; the extra “E” means electrical erase. Assuming all ROMs are nonerasable; modern nonvolatile memories include erasable variants. Final Answer:EPROM

Question 2

RAM diagnostics — interpreting the checkerboard test When a RAM module passes a checkerboard pattern memory test, which conclusion is most appropriate?

Accepted Answer

Introduction / Context:Memory diagnostics use test patterns to expose stuck-at and coupling faults. The checkerboard test writes alternating 1s and 0s across memory (e.g., 0xAA and 0x55 patterns), stressing both data lines and cell adjacency. Understanding the meaning of a “pass” helps with quick triage of suspected memory issues. Given Data / Assumptions: Checkerboard patterns: 1010… (0xAA) and 0101… (0x55), sometimes with address variations. RAM under test supports both write and read operations. Passing indicates correct storage and retrieval of these patterns. Concept / Approach:If the module stores both alternating patterns and reads them back without errors, many common failures (stuck-at-0, stuck-at-1, simple coupling) are unlikely. While not an exhaustive proof of perfection, it is a strong positive indicator, hence “probably good.” Step-by-Step Solution:Write checkerboard pattern A to all locations; read back and verify.Write inverse checkerboard pattern B; read back and verify.Both verifications succeed → module likely healthy. Verification / Alternative check:Additional patterns (walking 1s/0s, address tests, March algorithms) can further validate timing and address/data-line integrity to increase confidence beyond “probably good.” Why Other Options Are Wrong: “Only 1s” or “only 0s”: Passing checkerboard disproves these extremes. “Faulty”: Contradicts a clean pass on a stress-inducing pattern. Common Pitfalls: Assuming a single test guarantees perfection; combine multiple patterns for robust assurance. Ignoring marginal timing issues that might only appear at temperature or at-speed testing. Final Answer:It is probably good.

Question 3

DRAM cell refresh — common refresh period For mainstream dynamic RAM (DRAM) devices, which of the following is the typical refresh period used to retain data stored on capacitive cells?

Accepted Answer

Introduction / Context:DRAM stores each bit as charge on a tiny capacitor, which leaks over time. To prevent data loss, each row must be periodically refreshed (read and rewritten). Knowing the customary refresh period is essential for memory controller design and performance analysis. Given Data / Assumptions: DRAM requires periodic refresh of all rows. Common period for legacy and many commodity parts is approximately 64 ms (some extended-temp parts require 32 ms). Refresh can be distributed across the interval to reduce performance impact. Concept / Approach:The refresh interval defines how often all rows must be accessed to maintain charge. Controllers schedule refresh commands such that every row is refreshed at least once during the specified 64 ms window, balancing data integrity and bandwidth. Step-by-Step Solution:Identify the standard window: 64 ms for typical operating temperatures.Map rows to refresh cycles: e.g., 8K rows → 8K refreshes per 64 ms.Controller issues periodic refresh at intervals (for 8K rows, ~7.8 µs between refreshes). Verification / Alternative check:JEDEC specifications and device datasheets list tREFI (refresh interval) such that all rows are refreshed within 64 ms under normal temperature ranges, confirming the common value. Why Other Options Are Wrong: 2 µs / 64 µs: Far too frequent for full-array refresh; would waste bandwidth. 2 ms: Too short versus typical spec and not a standard whole-array interval. Common Pitfalls: Confusing tREFI (interval between refresh commands) with the total 64 ms window. Not accounting for reduced refresh windows (e.g., 32 ms) at high temperature grades. Final Answer:64 ms

Question 4

ROM data retention characteristic ROM devices retain their stored data under which power condition?

Accepted Answer

Introduction / Context:Read-only memories (ROM, PROM, EPROM, EEPROM/Flash) are nonvolatile, meaning they retain information without continuous power. This property distinguishes them from volatile memories like SRAM and DRAM, which lose data when power is removed (unless backed up). Given Data / Assumptions: Nonvolatile memory is intended to preserve firmware/configuration across power cycles. ROM family includes factory-programmed (mask ROM), field-programmable (PROM/EPROM), and electrically erasable variants (EEPROM/Flash). Concept / Approach:The definition of nonvolatile is data retention with power removed. Hence, the key advantage of ROM-type devices is that they store code or constants even when the system is off, enabling bootstrapping and persistent configuration. Step-by-Step Solution:Identify ROM as nonvolatile storage.Nonvolatile → retains data without power.Therefore, data is retained when power is off. Verification / Alternative check:Device datasheets guarantee data retention over specified time/temperature with power removed (for EEPROM/Flash, often years to decades), confirming nonvolatility. Why Other Options Are Wrong: “Power is on”: Trivially true, but the defining feature is retention with power off. “System is down”: Ambiguous wording; what matters is power at the device pins. “All of the above”: Overbroad; only “power is off” captures the defining trait. Common Pitfalls: Confusing ROM with battery-backed RAM; both may retain data across outages, but by different means. Assuming all nonvolatile devices are infinitely durable; write/erase cycles and retention times are finite. Final Answer:Power is off

Question 5

Driving multiple TTL loads from a bus — memory interface requirement Because CPUs and memory ICs are typically specified to drive only one standard TTL load, what must be added if several inputs are being driven from the same bus line?

Accepted Answer

Introduction / Context:Fan-out is the number of standard logic inputs that one output can reliably drive. Many microprocessors and memory parts are rated for about one standard TTL load. When a bus must fan out to multiple destinations, signal integrity and timing can degrade unless additional drivers are used. Given Data / Assumptions: One bus line must feed several inputs. Each load adds input capacitance and DC current draw. The original device has limited fan-out capability. Concept / Approach:Buffering interposes a high-drive stage with stronger output currents (IOH/IOL) and lower output impedance to maintain valid logic levels and edge rates. Bus transceivers or dedicated line drivers are standard solutions on address/data buses and control signals. Step-by-Step Solution:Assess fan-out requirement vs. device rating.If multiple loads exceed rating, insert a buffer/driver.Use proper direction control if bidirectional (transceiver). Verification / Alternative check:Datasheets specify VOL/VOH at given currents. If total load exceeds spec, VOH/VOL may violate thresholds; a buffer restores margins and preserves timing. Why Other Options Are Wrong: Decoded: Address decoding selects which device responds; it does not increase drive strength. Addressed/Stored: Not relevant to electrical drive capability. Common Pitfalls: Ignoring capacitive loading and long traces that slow edges and cause ringing. Assuming pull-ups alone fix drive issues; active buffering is often required. Final Answer:Buffered

Question 6

Write-cycle timing — correct sequence for a memory write Which timing sequence correctly describes a synchronous write operation to memory?

Accepted Answer

Introduction / Context:A memory write requires that the target address and the data to be written both meet setup and hold times around the write strobe (WR). Getting the order wrong can corrupt data or write to the wrong location. Understanding the canonical sequence is foundational for timing analysis and bus design. Given Data / Assumptions: Signals: Address, Data, Write Enable (WE or /WR). Setup time: Address and Data must be stable prior to the active write edge or level. Hold time: Address and Data must remain stable briefly after the write event. Concept / Approach:The correct sequence is: present the address, present valid data, then assert the write control to store the data at that address. Finally, deassert the write control and release or change bus lines after hold-time requirements are met. A “read pulse” never stores data, so any option saying that is incorrect. Step-by-Step Solution:tSU(Address, Data) → Address and Data valid.Assert /WR (active level or edge) to latch data into memory.tH(Address, Data) → Maintain stability for hold time; then deassert /WR. Verification / Alternative check:SRAM/DRAM datasheets show timing diagrams where address/data precede the write strobe, ensuring the device captures the intended value at the intended location. Why Other Options Are Wrong: Address then data then read pulse: read pulse does not write. Write pulse first: violates setup; may write garbage or to wrong address. Data then write then address: violates both address and data setup requirements. Common Pitfalls: Ignoring bus turnaround times when switching from read to write cycles. Overlooking that some memories require chip enable and output enable states to be inactive during writes. Final Answer:Assert the address and place valid data on the data bus; then apply the active write pulse to store the data

Question 7

RAM speed — key timing parameters Which timing parameters primarily set a RAM device’s operating speed?

Accepted Answer

Introduction / Context:RAM performance is defined by how fast it can complete read and write cycles. Datasheets provide multiple parameters, but two composite timings dominate throughput: read cycle time and write cycle time. Recognizing them helps you estimate maximum sustainable bandwidth. Given Data / Assumptions: tRC: Read Cycle time (minimum time between successive valid reads). tWC: Write Cycle time (minimum time between successive valid writes). Other parameters specify internal delays to outputs or control pin setup/hold relationships. Concept / Approach:Throughput is bounded by how quickly back-to-back operations can finish. tRC and tWC capture the end-to-end latency constraints for reads and writes. While access time (tACC, tAA) and output delay (tCO, tOD) are important, the full cycle times dictate the maximum operation frequency in many simple interfaces. Step-by-Step Solution:Identify high-level throughput constraints: cycle times.Recognize tRC (reads) and tWC (writes) as the primary limits.Therefore, these two parameters primarily determine operating speed. Verification / Alternative check:Timing diagrams show that even if access time is short, violating tRC/tWC results in unstable or undefined operations; thus cycle times cap the effective frequency of consecutive operations. Why Other Options Are Wrong: tACC, tAA, tACS, tCO, tOD: Important, but they are subcomponents; they do not alone define the maximum sustained read/write rate. Common Pitfalls: Equating fast access time with high throughput without considering cycle time constraints. Ignoring bus turnaround and control pin setup/hold that also factor into tRC/tWC. Final Answer:tRC and tWC

Question 8

Core advantage of semiconductor RAM What is the principal advantage of semiconductor RAM compared with sequential-access memories like magnetic tape?

Accepted Answer

Introduction / Context:The term RAM stands for Random Access Memory. Unlike sequential-access media (tapes, some serial EEPROM streams), RAM allows direct access to any address in essentially constant time. This property defines how CPUs fetch instructions and data efficiently during program execution. Given Data / Assumptions: RAM is volatile in common SRAM/DRAM forms (data lost when power is removed). “Random access” means time to access location N is about the same as location M. Sequential media require stepping through intervening data to reach a location. Concept / Approach:The core advantage is addressable immediacy: processors can read or write any word without first scanning through earlier addresses. While RAM is also fast, “random access” is the defining advantage compared to sequential storage; speed is a beneficial consequence in most implementations but is not the naming rationale. Step-by-Step Solution:Identify what “random access” implies: O(1)-like access across addresses.Contrast with sequential access: must traverse data sequentially to reach target.Therefore, the principal advantage is the ability to be randomly accessed. Verification / Alternative check:Computer architecture texts emphasize that caches and main memory rely on random-access properties to supply instructions/data at arbitrary addresses rapidly, enabling general-purpose computing. Why Other Options Are Wrong: “Retain data without power”: That is nonvolatile memory (ROM/Flash), not standard RAM. “Rapid read/write”: Often true, but the term “RAM” specifically highlights the random-access nature. “Sequentially accessed”: This describes tapes and some serial devices, not RAM. Common Pitfalls: Confusing RAM's volatility with its access method; many forms of RAM are fast but volatile. Assuming the name derives from speed; it derives from access pattern. Final Answer:Be randomly accessed

Question 9

Memory technologies — relative bit-cell size In general, which technology has the smallest bit-cell area and which has the largest, when comparing common integrated memory types?

Accepted Answer

Introduction / Context:Integrated memories implement one logical bit using a “cell.” Different memory families use different devices for the cell (for example, a transistor-capacitor in DRAM or multiple transistors in SRAM). Cell design directly affects density (bits per mm^2), cost, power, and speed. This question compares typical, mainstream implementations used in digital systems. Given Data / Assumptions: We are comparing mainstream mask ROM, DRAM, Flash/EEPROM, and SRAM bit-cell sizes on silicon. “Smallest” means highest density; “largest” means lowest density for a single stored bit. Conventional read-only mask ROM is implemented with the fewest devices per bit. Concept / Approach: Mask ROM encodes data as the presence or absence of a device or connection, achieving extremely compact cells. DRAM uses 1 transistor + 1 capacitor per bit, also very dense but larger than simple ROM geometry. Nonvolatile Flash/EEPROM cells require special structures (floating gates, tunneling oxides), so area is moderate. SRAM typically needs 6 or more transistors per bit for static storage, making it the least dense (largest cell area). Step-by-Step Solution: Identify highest density (smallest cell): mask ROM < DRAM < Flash/EEPROM < SRAM.Therefore, smallest = mask ROM; largest = SRAM.Match to the provided options: “mask ROM, SRAM.” Verification / Alternative check: Textbooks and vendor datasheets consistently report SRAM density far below DRAM/ROM due to multi-transistor cells, while mask ROM is historically the densest because it eliminates write circuitry entirely. Why Other Options Are Wrong: EEPROMs, Flash: these are denser than SRAM but not denser than mask ROM. SRAM, mask ROM: reverses the true order. DRAM, PROM: DRAM is not the smallest compared to mask ROM; “PROM” is a family term and not necessarily the largest. Common Pitfalls: Confusing access speed (often fastest for SRAM) with density (lowest for SRAM). Assuming all ROMs have identical density; mask-programmed ROMs are typically most compact. Final Answer: mask ROM, SRAM

Question 10

Characteristics of an ideal memory device Which statement best describes an “ideal” memory for digital systems?

Accepted Answer

Introduction / Context:Designers dream of an “ideal” memory that combines the best traits of today’s RAM and nonvolatile technologies. Understanding these traits helps explain why systems mix multiple memory types (SRAM cache, DRAM main memory, Flash/EEPROM storage). Given Data / Assumptions: Ideal memory is a conceptual target, not a single existing device. Desirable traits include capacity, nonvolatility, and in-system read/write capability. No trade-offs for speed, endurance, or power are implied in the idealization. Concept / Approach: High capacity minimizes cost per bit. Nonvolatility preserves data without power. In-system read/write capability means byte or word programmability without special equipment, enabling firmware updates and general data storage under normal operating conditions. The ideal memory would combine all these benefits simultaneously. Step-by-Step Solution: List key attributes: capacity, nonvolatile retention, and easy read/write.Check options: A, B, and C are all desirable and none are mutually exclusive.Therefore, the ideal memory has all the above characteristics → option D. Verification / Alternative check: Real devices: DRAM offers capacity but is volatile; SRAM offers speed but low density; Flash/EEPROM offer nonvolatility and in-system programming but slower writes. The ideal merges these strengths. Why Other Options Are Wrong: Only capacity: ignores data loss on power removal. Only nonvolatility: ignores practical write needs. Only in-system R/W: without capacity and retention, it falls short. Common Pitfalls: Equating “ideal” with a single commercial part; actual devices involve trade-offs. Final Answer: has all of the above characteristics

Question 11

Reading logic symbols — output bubbles/triangles In the shown memory/logic device, small inverted triangles (inverters) appear at the outputs. What do they indicate about the outputs?

Accepted Answer

Introduction / Context:Schematic symbols use small shapes to communicate logic polarity. A tiny inversion symbol at a pin tells you whether the external “active” level is a logical LOW or HIGH. This is crucial when interfacing memory or logic outputs to downstream circuits and buses. Given Data / Assumptions: The symbol shows a small inversion marker (often a small triangle with a bubble, or a bubble) placed at the output pins. We are to infer the output's active polarity. No other special drive symbols (e.g., tri-state enable bars) are indicated. Concept / Approach: An inversion indicator denotes logical inversion between the internal node and the external pin. When placed on an output, it signals that the output is asserted at logical 0 (active-LOW). Datasheets often label such pins with a bar over the name (e.g., OE̅) or a trailing “#” or “/”. Step-by-Step Solution: Identify inversion indicator at the output.Outputs that are “active” when LOW are said to be active-LOW.Therefore, the inverters indicate active-LOW outputs. Verification / Alternative check: Cross-check with common logic symbols: input or output bubbles consistently mean active-LOW polarity; triangles alone can denote buffers or amplifiers but a bubble denotes inversion/active-LOW. Why Other Options Are Wrong: High fan-out claim is a drive strength attribute, not a symbol for inversion. “Change-detect” behavior is unrelated to inversion symbols. Tristate is typically shown with an enable pin (often active-LOW) and not merely with inversion at outputs. Common Pitfalls: Confusing tri-state capability with active-LOW polarity indicators. Final Answer: They represent inverters and mean that the outputs are active-LOW.

Question 12

Mask ROM programming concept Which statement correctly describes how a bit is stored in a mask ROM cell?

Accepted Answer

Introduction / Context:Mask ROMs are programmed during fabrication by including or omitting device connections. The readout circuitry interprets the presence of a programmed transistor path as a logical 1 or 0 depending on the architecture. A common MOS mask ROM stores a 1 by providing a transistor gate connection to the word line (address line). Given Data / Assumptions: We are considering a typical MOS mask ROM bit-cell. Readout uses a pull-up or pull-down network that senses whether a device is present and enabled by the addressed word line. Conventions can vary, but a standard depiction maps the present transistor (gate tied to word line) to a logical 1 at the sense node. Concept / Approach: In fabrication, a “mask option” either connects a transistor’s gate to the word line or leaves it unconnected. If connected, when the word line is asserted, the transistor conducts, indicating a stored 1 (with suitable sense circuitry). If left unconnected, the path is absent and the bit reads as 0. Step-by-Step Solution: Program bit=1 → include transistor gate connection to word line.Program bit=0 → omit the connection (or include a complementary path per design).Therefore, option C correctly describes a common MOS mask ROM practice. Verification / Alternative check: Standard cell diagrams in introductory VLSI and memory texts show presence/absence of the gate connection controlling the read path; this is the essence of mask programming. Why Other Options Are Wrong: Options A and B refer to “bipolar base connections”—not typical for MOS mask ROM explanation. Option D reverses the usual MOS convention in many pedagogical treatments. Common Pitfalls: Assuming all mask ROMs use identical logic polarity; vendors may swap conventions, but the question targets the common MOS description. Final Answer: A 1 is stored by connecting the gate of a MOS cell to the address line.

Question 13

Static RAM (SRAM) vs. Dynamic RAM (DRAM) What is the basic operational difference between SRAM and DRAM in terms of data retention?

Accepted Answer

Introduction / Context:SRAM and DRAM are the two dominant volatile memory types in digital systems. Their cell structures create distinctly different behaviors for data retention, power, speed, and density. Understanding refresh is essential for system timing and power design. Given Data / Assumptions: SRAM uses multi-transistor latch cells that hold state as long as power is present. DRAM stores charge on a tiny capacitor, which leaks over time. Refresh is a periodic read/restore action necessary for DRAM capacitors. Concept / Approach: Because DRAM charge decays, controllers must perform refresh cycles to read and rewrite each row before the charge falls below a readable threshold. SRAM cells, being bistable latches, do not need refresh; they maintain 0 or 1 continuously under power, enabling faster random access at the cost of area. Step-by-Step Solution: Identify which memory needs periodic maintenance for data retention → DRAM.Identify which memory does not require refresh under power → SRAM.Thus: Dynamic RAM must be refreshed; Static RAM does not. Verification / Alternative check: Every DRAM datasheet specifies refresh intervals (e.g., all rows within 64 ms). SRAM datasheets do not contain refresh timing; their limits revolve around access time and power. Why Other Options Are Wrong: Option A is the inverse of reality. Option B ignores fundamental architectural differences. Common Pitfalls: Equating nonvolatility with “no refresh.” Both SRAM and DRAM are volatile; neither retains data when power is removed. Final Answer: Dynamic RAM must be refreshed, static RAM does not.

Question 14

Address space sizing With an 8-bit address code, how many unique memory locations can be selected?

Accepted Answer

Introduction / Context:Address lines select locations in memory using binary codes. The number of unique addresses depends on the number of address bits. This is a foundational calculation in digital design and computer architecture. Given Data / Assumptions: Number of address bits n = 8. Each unique address maps to one location. Binary combinations are counted as powers of 2. Concept / Approach: The number of unique codes represented by n bits is 2^n. Therefore, an 8-bit address field can address 2^8 locations. This relationship scales directly (e.g., 16 bits → 2^16 locations, etc.). Step-by-Step Solution: Compute total addresses = 2^n.For n = 8: 2^8 = 256.Therefore, 256 distinct memory locations can be selected. Verification / Alternative check: Check extremes: with 1 bit you can select 2 locations; doubling bits squares capacity. 8 bits yielding 256 is consistent with this rule. Why Other Options Are Wrong: 8 locations: corresponds to 3 address bits. 65,536 locations: requires 16 address bits. 131,072 locations: requires 17 address bits. Common Pitfalls: Confusing bytes of data per location with number of locations. Address bits count locations, independent of data width. Final Answer: 256 locations in memory

Question 15

Types of ROM — factory mask options Which ROM type must be custom programmed by the manufacturer during fabrication (i.e., mask-programmed)?

Accepted Answer

Introduction / Context:Read-Only Memory (ROM) families differ in when and how the data pattern is written. Some are field-programmable; others are fixed at the factory. Understanding these differences informs cost, lead time, and flexibility in product design. Given Data / Assumptions: Mask ROM is defined by photolithographic masks that include or omit connections. EPROM/EEPROM/Flash are field- or lab-programmable after fabrication. “ROM” as a generic term is ambiguous; the question targets the specific subtype requiring factory customization. Concept / Approach: Mask ROM content is permanent and set by the silicon masks before wafer processing. This yields very high density and low cost per unit at high volumes, but it sacrifices flexibility and requires substantial NRE (nonrecurring engineering) for masks. Step-by-Step Solution: Identify the ROM that is not programmable in the field → mask ROM.EPROM/EEPROM can be programmed and (for EEPROM) electrically erased and reprogrammed.Therefore, the correct choice is “mask ROM.” Verification / Alternative check: Device datasheets and manufacturing flows clearly distinguish mask-programmed ROM from one-time or reprogrammable ROM families. Why Other Options Are Wrong: Generic “ROM” does not specify factory programming. EPROM and EEPROM are user-programmable after fabrication. Common Pitfalls: Confusing one-time programmable (OTP) EPROM with mask ROM; OTP EPROM is field-programmable once, not mask-set at the factory. Final Answer: mask ROM

Question 16

Key DRAM characteristic — refresh requirement Which statement is a fundamental characteristic of dynamic RAM (DRAM) devices?

Accepted Answer

Introduction / Context:DRAM cells store bits as charge on tiny capacitors, which leak over time. System designers must account for this by scheduling refresh operations. Recognizing this requirement is central to memory controller design and timing closure. Given Data / Assumptions: DRAM cells = 1 transistor + 1 capacitor per bit. Charge leakage necessitates periodic refresh of all rows. Refresh frequency is specified in datasheets (for example, all rows within 32–64 ms). Concept / Approach: Refreshing reads a row and immediately rewrites it, restoring the stored charge in each capacitor. This is independent of normal CPU access. Without refresh, data decays to an indeterminate state, causing errors. Step-by-Step Solution: Identify the unique feature of DRAM operation → periodic refresh.Reject statements unrelated to refresh or incorrectly worded about “dynamic inputs.”Choose option B as the correct DRAM characteristic. Verification / Alternative check: Comparing with SRAM: no refresh is required. With nonvolatile memories: no refresh under power loss, but different constraints (erase/write cycles). Why Other Options Are Wrong: Constantly changing input: incorrect—input activity is unrelated to data retention. “Broader dynamic range”: not a standard memory term. “Simpler devices”: cell may be simple, but system requirements (refresh logic) are not the defining characteristic. Common Pitfalls: Assuming normal read/write accesses by the CPU alone will adequately refresh the entire array; controllers must guarantee all rows are refreshed in time. Final Answer: DRAMs must be periodically refreshed in order to be able to retain data.

Question 17

Purpose of DRAM refresh cycles Why is a refresh cycle necessary in dynamic RAM (DRAM)?

Accepted Answer

Introduction / Context:Unlike SRAM, DRAM uses capacitors to store bits. Due to leakage, the stored charge decays, so periodic refresh is required to maintain data validity. Understanding what refresh actually does prevents misconceptions about DRAM behavior. Given Data / Assumptions: DRAM cell = capacitor that slowly discharges. Refresh consists of reading and writing back the same data. No flip-flops are used inside the DRAM array for data retention. Concept / Approach: During refresh, the sense amplifiers detect the small residual charge and then restore a full charge to represent a 1 (or zero level as required), effectively “recharging” each capacitor so that data persists for the specified retention time. Step-by-Step Solution: Recognize the physical mechanism: leaking capacitors.Determine refresh purpose: restore the correct charge level.Thus, refresh keeps (replenishes) the charge on the capacitor cells. Verification / Alternative check: DRAM timing diagrams show refresh cycles that access rows even without CPU requests, ensuring each row is periodically restored. Why Other Options Are Wrong: Flip-flop references (A and B) are inapplicable; DRAM cells are not flip-flops. Discharges the capacitors (C) is the opposite of the goal—refresh recharges them. Common Pitfalls: Believing ordinary accesses always cover all rows. Controllers must guarantee refresh across the full array within the retention window. Final Answer: The refresh cycle keeps the charge on the capacitor cells.

Question 18

Recognizing valid memory types Which of the following is NOT a recognized memory type designation in standard usage?

Accepted Answer

Introduction / Context:Digital systems commonly reference memory by family names: RAM (random access memory), ROM (read-only memory), EPROM, EEPROM, and Flash. Some acronyms are informal or uncommon and can cause confusion in specifications and parts lists. Given Data / Assumptions: We compare the listed acronyms against widely used industry terms. RAM, ROM, EEPROM are standard. “FPROM” is not a standard, widely adopted designation; when used informally it may ambiguously refer to “Flash PROM,” but this is not a canonical device class name. Concept / Approach: The question asks for the nonstandard option. RAM and ROM are umbrella categories. EEPROM (Electrically Erasable Programmable Read-Only Memory) is a well-defined nonvolatile memory. “FPROM” does not represent a distinct, universally recognized memory family in formal datasheets; the accepted terms are EPROM and Flash (NOR/NAND), not “FPROM.” Step-by-Step Solution: Identify recognized categories: RAM, ROM, EEPROM → valid.Identify the outlier acronym lacking standard definition → FPROM.Therefore choose FPROM as NOT a standard memory type name. Verification / Alternative check: Component catalogs and manufacturer datasheets list SRAM, DRAM, ROM, PROM, EPROM, EEPROM, and Flash families; “FPROM” is not presented as a mainstream classification. Why Other Options Are Wrong: RAM: volatile memory umbrella (SRAM/DRAM). ROM: nonvolatile family umbrella (mask ROM, PROM, EPROM, EEPROM, Flash). EEPROM: established nonvolatile type. Common Pitfalls: Assuming every initialism ending with “PROM” is standard; verify with datasheets and standards. Final Answer: FPROM

Question 19

In dynamic RAM (DRAM) design, what are the basic refresh modes used to periodically restore the stored charge in the memory cells?

Accepted Answer

Introduction / Context:Dynamic RAM (DRAM) stores each bit as charge on a tiny capacitor that leaks over time. To prevent data loss, DRAM must be refreshed at regular intervals. This question checks your understanding of the fundamental refresh strategies commonly referenced in memory system design and data sheets. Given Data / Assumptions: Technology: DRAM (not SRAM). Cells are leaky capacitors that require periodic refresh within a specified retention time. We are considering the standard, widely taught refresh schemes. Concept / Approach:Two basic refresh schemes are widely cited: burst (sometimes called RAS-only or burst-of-rows refresh) and distributed refresh. Burst refresh refreshes many or all rows in a tight sequence during a maintenance window. Distributed refresh spreads refresh commands evenly over time so normal accesses are less impacted. While you may encounter additional vendor terms like hidden/self refresh, the foundational pair in many curricula is burst and distributed refresh. Step-by-Step Solution:Identify the goal: keep every row refreshed within the maximum refresh interval (e.g., 64 ms).Understand burst refresh: issue refresh commands back-to-back to cover many rows rapidly during idle periods.Understand distributed refresh: interleave refresh commands periodically so performance impact is smoothed over time.Conclude the basic modes: burst refresh and distributed refresh. Verification / Alternative check:Vendor timing diagrams show auto-refresh commands that can be scheduled in groups (burst) or interspersed among normal cycles (distributed). Both satisfy the row refresh count requirement within the retention window. Why Other Options Are Wrong:Burst refresh: incomplete by itself as the question asks for the basic mode(s), plural.Distributed refresh: also incomplete alone in this context.Open refresh: not a standard term for a DRAM mode.Hidden refresh only: hidden/self refresh exists, but it is not the canonical pair being asked. Common Pitfalls:Mixing SRAM concepts (which do not need refresh) with DRAM, and confusing vendor-specific names with textbook categories. Also, forgetting that any valid scheme must ensure every row is refreshed in time. Final Answer:Burst refresh and distributed refresh

Question 20

In computer architecture, what components are considered part of the main (primary) memory of a computer system, as opposed to secondary storage?

Accepted Answer

Introduction / Context:Main memory, also called primary memory, is the directly addressable memory space that the CPU uses to fetch instructions and data at electronic speeds. This question distinguishes primary memory from secondary storage devices like hard drives and optical media. Given Data / Assumptions: Main memory is directly addressable by the processor. Secondary storage (e.g., HDD, SSD, CD-ROM) is non-volatile but not directly accessed at CPU instruction cycle speed. ROM refers to non-volatile memory mapped for bootstrap/firmware. Concept / Approach:Primary memory typically includes RAM (Random Access Memory), which is volatile and holds the currently executing code and working data, and ROM (Read-Only Memory), which stores firmware/boot code. While modern systems may load firmware from flash, the conceptual pairing for main memory remains RAM + ROM in foundational terminology. Disks and optical media are classified as secondary storage. CMOS is usually referenced as a small configuration memory powered by a battery; it is not the main memory. Step-by-Step Solution:Identify primary memory elements: RAM (volatile, read/write) and ROM (non-volatile, firmware).Exclude storage devices: HDD, SSD, CD-ROM → secondary storage.Exclude CMOS NVRAM used for BIOS settings; it is not the system’s main addressable working memory.Therefore, main memory = RAM and ROM. Verification / Alternative check:Introductory computer organization texts consistently separate primary memory (RAM/ROM) from mass storage (HDD/SSD/optical). System block diagrams show RAM/ROM on the memory bus, while disks connect via storage controllers. Why Other Options Are Wrong:Hard drive and RAM / CD-ROM and hard drive: mix primary and secondary; not both are main memory.CMOS and hard drive: neither is the main addressable execution memory.Cache and SSD only: cache is part of the memory hierarchy but not the complete main memory; SSD is secondary storage. Common Pitfalls:Equating “storage capacity” with “main memory” and assuming anything that stores data is main memory. Always distinguish bus attachment and access latency. Final Answer:RAM and ROM

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