Question 1

System buses – what is the primary purpose of tri-state or open-collector memory outputs when multiple devices share a common bus?

Accepted Answer

Introduction / Context: Many memory chips connect to a shared data bus. If more than one device attempts to drive the lines simultaneously, contention can damage parts or corrupt data. Tri-state and open-collector outputs enable safe sharing by ensuring only one device actively drives the bus at a time. Given Data / Assumptions: Multiple memory or peripheral devices connected to a single data bus. Chip select and output enable control which device is active. Bus pull-ups (for open-collector/drain) or high-impedance state (for tri-state) are available. Concept / Approach: A tri-state output has three states: logic 0, logic 1, and high-impedance (Z). When not selected, the device goes to Z, effectively disconnecting from the bus. An open-collector/drain output can only pull the line low; a shared pull-up resistor brings it high. Wired-OR/AND combinations become possible without active conflicts, enabling multiple devices to interface safely on common lines. Step-by-Step Solution: 1) Assert chip select on the desired memory; others remain deselected.2) The selected device enables its outputs; non-selected devices present Z (tri-state) or remain passive (open-collector/drain).3) Bus carries valid data from the one active source without contention.4) Release control to return the bus to idle for the next master/slave. Verification / Alternative check: Timing diagrams show OE controlling Z vs active drive. I2C uses open-drain sharing with pull-ups, demonstrating conflict-free multi-device operation. Why Other Options Are Wrong: They do not address contention prevention: speed, current, or internal simplicity are side effects at best, not the core reason. Common Pitfalls: Forgetting to deassert OE/CS on inactive devices; neglecting proper pull-ups for open-drain buses. Final Answer: isolate devices connected to a common bus

Question 2

Nonvolatile families – which device is user-programmable but cannot be erased and reprogrammed afterward?

Accepted Answer

Introduction / Context: Read-only memory technologies vary in how and when data is written. Recognizing which device is one-time programmable is important for cost, security, and field-update decisions. PROMs are intended for a single programming event after fabrication and then behave as fixed ROMs. Given Data / Assumptions: User needs to write content once post-manufacture. No erasure mechanism exists in the target technology. Functionally read-only after programming. Concept / Approach: PROM (Programmable ROM) uses fuses/antifuses to permanently set bits. Once programmed, the physical change cannot be undone electrically or optically. By contrast, EPROMs can be UV-erased; EEPROMs and Flash are electrically erasable and reprogrammable. Mask ROMs are factory-set and not user-programmable at all. Step-by-Step Solution: 1) Exclude mask ROM (not user-programmable).2) Exclude EPROM/EEPROM/Flash (all erasable by UV or electrically).3) Identify PROM as user-programmable, one-time device.4) Conclude PROM matches the description. Verification / Alternative check: PROM datasheets describe “OTP” operation and lack any erase instructions, unlike EPROM/EEPROM/Flash parts. Why Other Options Are Wrong: Mask ROM is not programmable by the user; EPROM/EEPROM/Flash are erasable and rewritable. Common Pitfalls: Confusing PROM with EPROM due to similar names; the key difference is erasability. Final Answer: PROM

Question 3

Volatile main memory – which memory technology requires periodic refreshing to avoid data loss?

Accepted Answer

Introduction / Context: Volatile memories lose data without power, but their internal storage mechanisms differ. Dynamic random-access memory (DRAM) stores bits as charge on tiny capacitors that leak over time. Recognizing which memory requires refresh is basic knowledge for system timing and controller design. Given Data / Assumptions: Commodity main memory in PCs and many SoCs is DRAM. Refresh is performed by the memory controller automatically. Static RAM (SRAM) stores data in bistable latches, needing no refresh. Concept / Approach: DRAM cells are a capacitor plus access transistor. Leakage causes charge to decay, so rows must be periodically read and rewritten (refresh) within a retention window (for example, every 64 ms). SRAM cells, built from cross-coupled inverters, hold state as long as powered and do not need refresh. Nonvolatile memories (ROM/EPROM/EEPROM) retain data without power and also do not need refresh. Step-by-Step Solution: 1) Identify storage mechanism of candidates.2) Determine whether leakage mandates refresh.3) Only DRAM requires periodic refresh among the listed options.4) Select DRAM as correct. Verification / Alternative check: DRAM datasheets specify refresh commands (AUTO REFRESH/SELF REFRESH) and retention times; SRAM datasheets have no such requirement. Why Other Options Are Wrong: SRAM is volatile but not refreshed; ROM/EPROM/EEPROM are nonvolatile and require no refresh either. Common Pitfalls: Assuming all volatile memories need refresh; only DRAM does because it stores charge rather than a stable latch state. Final Answer: DRAM

Question 4

Memory test methods – the checkerboard pattern test is commonly used to test which class of memory?

Accepted Answer

Introduction / Context: Memory testing uses structured data patterns to uncover specific fault modes. The checkerboard pattern alternates 1s and 0s in adjacent cells to expose coupling, pattern-sensitive, and addressing faults. Knowing which memory this targets helps in diagnostics and production test flows. Given Data / Assumptions: Goal: detect disturbances between neighboring cells and lines. Device under test is byte/word-addressable volatile memory. Read-back comparison is available at full speed. Concept / Approach: The checkerboard test writes 0xAA (10101010) and 0x55 (01010101) patterns across memory, then reads back to detect errors. Because adjacent bits in the same word and adjacent addresses alternate values, the test stresses cell interactions and sense line integrity—classic concerns in RAM arrays. ROM contents are fixed and cannot be overwritten with patterns, making the checkerboard unsuitable there; EEPROM/Flash have limited endurance and slower writes, making the test impractical as a routine screen. Step-by-Step Solution: 1) Fill memory with 0xAA at all addresses; read/verify.2) Fill with 0x55; read/verify.3) Optionally apply address-walking patterns to catch decoder faults.4) Log mismatches to locate failing cells/lines. Verification / Alternative check: Standard RAM test suites (March tests, GALPAT) include checkerboard as a quick screen specifically for RAM fault models. Why Other Options Are Wrong: ROM cannot be overwritten; EEPROM/Flash endurance constraints discourage repetitive pattern tests; FPLA is a programmable logic array, not a byte-addressable RAM target. Common Pitfalls: Treating checkerboard as sufficient alone; comprehensive testing also includes walking 1/0 and March algorithms. Final Answer: RAM

Question 5

Serial access devices – a memory that is accessed one location after another in sequence is best described as a ________.

Accepted Answer

Introduction / Context: Not all storage devices provide random access. Serially accessed devices present data in a fixed order, which influences latency and interface design. Recognizing examples helps match devices to applications such as streaming and serializers/deserializers. Given Data / Assumptions: Access proceeds in a fixed sequence rather than by arbitrary addressing. Output at any instant is the “next” stored value. Device may be implemented with flip-flops or dynamic techniques. Concept / Approach: A shift register stores bits in stages and shifts them left or right on clock edges, presenting or sampling one bit per step. This is the archetype of serial access storage. In contrast, RAM (read/write memory) is random access; ROM is random access (read-only); PLDs implement logic, not serial storage; associative caches access by content rather than sequence. Step-by-Step Solution: 1) Identify device that inherently outputs data in sequence on each clock → shift register.2) Exclude RAM/ROM because they support addressing any location directly.3) Exclude PLD/associative cache due to different access paradigms.4) Select “shift register.” Verification / Alternative check: Serial EEPROMs present bytes serially over SPI/I2C, but internally are random access memories; a pure shift register is the canonical serial access memory used for delay lines and serializers. Why Other Options Are Wrong: ROM and read/write RAM are random access; PLDs implement combinational/sequential logic, not serial storage; associative caches are content-addressable, not serial. Common Pitfalls: Confusing serial interface with serial access; some RAMs use serial interfaces but allow random addressing internally. Final Answer: shift register

Question 6

Module packaging – which statement about a DIMM (dual inline memory module) is accurate regarding its connector contacts and data path?

Accepted Answer

Introduction / Context: Memory modules evolved from SIMMs (single inline memory modules) to DIMMs (dual inline memory modules) to support wider data buses and higher bandwidth. Knowing the physical and electrical differences helps in correctly identifying modules and motherboard compatibility. Given Data / Assumptions: SIMMs historically had 30 or 72 contacts with mirrored signals on each side. DIMMs provide distinct contacts on the two sides of the edge connector. Wider data paths reduce the number of modules needed for a given bus width. Concept / Approach: A DIMM has separate electrical contacts on both faces of the connector (hence “dual inline”), allowing more pins and therefore wider data and control interfaces (for example, 168-pin SDR, 184-pin DDR, 240-pin DDR2/DDR3, 288-pin DDR4/DDR5). SIMMs have contacts that are the same electrical node on both sides (“single inline”), offering fewer unique signals. Therefore, the accurate statement is that DIMMs have contacts on both sides enabling larger data paths. Step-by-Step Solution: 1) Distinguish “single” vs “dual” inline: mirror vs distinct contacts.2) Recognize result: more pins → wider data path and features.3) Match to answer choice describing both-sided contacts and larger paths.4) Select that statement. Verification / Alternative check: Motherboard memory slot specifications list pin counts corresponding to DIMM generations, confirming dual-sided distinct contacts and wider interfaces. Why Other Options Are Wrong: 30/72-pin packages belong to SIMMs; DIMMs do not have pins only on one side; capacity comparisons depend on generation, not SIMM vs DIMM; keying notches differ across generations and are not shared with SIMMs. Common Pitfalls: Assuming “pins on both sides” means mirrored signals; in DIMMs, they are distinct contacts, which is the key difference from SIMMs. Final Answer: has contact pins on both sides of the module for larger data paths

Question 7

Memory organization and chip count calculation: A 2147 static RAM device is organized as 4K × 1, meaning 4096 storage locations with 1 bit per location. How many identical 2147 RAM chips are required to construct an 8K × 8 memory module (8,192 addre…

Accepted Answer

Introduction / Context: Designers often need to build a larger memory from smaller integrated circuits. Understanding how to expand both word width (data bits per address) and depth (number of addresses) is fundamental to digital design and memory mapping. This problem asks how many 4K × 1 static RAM chips are needed to realize an 8K × 8 memory, a classic exercise that combines bit-width paralleling with depth expansion via banking or decoding. Given Data / Assumptions: Available chip: 2147 static RAM organized as 4K × 1 (4096 × 1 bit). Target memory: 8K × 8 (8192 addresses, each 8 bits wide). All chips are identical; ideal decoding and control signals are available. Ignore timing skew and fan-out limits; focus on count and organization. Concept / Approach: To build a wider word (more bits per address), place 1-bit devices in parallel so their data outputs form the multi-bit word. To build deeper memory (more addresses), place complete words in banks selected by an address decoder or bank-select logic. Total chip count = chips for width * banks for depth. Use powers-of-two relationships to determine address expansion cleanly. Step-by-Step Solution: 1) Width expansion: each 2147 provides 1 data bit; to get 8 bits per address, use 8 chips in parallel. These share all address lines; each contributes one bit (D0…D7).2) Depth expansion: each 2147 has 4K addresses; target is 8K, which is 2 × 4K. Therefore, create 2 banks of the 8-parallel set and select the active bank with a decoder.3) Chip count: width 8 chips per bank × depth 2 banks = 16 chips total.4) Control wiring: the decoder output drives the Chip Enable (or CS) of each bank; WE and OE fan out to all chips with proper buffering if needed. Verification / Alternative check: Compute in bits: target capacity = 8K × 8 = 8192 × 8 = 65,536 bits. One 4K × 1 chip stores 4096 bits. Number of chips needed = 65,536 / 4096 = 16, matching the bank-and-width reasoning. Why Other Options Are Wrong: “One” grossly underestimates capacity. “Four” equals 16,384 bits only. “Eight” yields 32,768 bits and provides either 8-bit width at only 4K depth or 8K depth at only 4-bit width, not the full 8K × 8. Common Pitfalls: Confusing width and depth expansion; forgetting that a 1-bit-wide chip requires 8 devices for an 8-bit word; trying to expand depth by wiring addresses incorrectly rather than using bank enables. Final Answer: Sixteen

Question 8

Address space expansion for RAM arrays: When increasing memory depth using a decoder and multiple RAM ICs, to which control/input pin of each memory should the decoder outputs be connected to select one device at a time?

Accepted Answer

Introduction / Context: Expanding memory depth means using several identical memory ICs as banks so that more addressable locations exist at the same word width. A decoder examines high-order address bits and activates exactly one bank for any given address range. Correctly wiring the decoder outputs to the memory control pins is critical to avoid bus contention and ensure correct operation. Given Data / Assumptions: Goal: expand address space (depth) using a decoder plus multiple RAM ICs. Each memory IC has Chip Enable (CE or /CS), Write Enable (WE or /WE), and Output Enable (OE or /OE). The system shares the same address and data buses across all banks. Concept / Approach: The decoder converts a subset of high-order address lines into one-hot control signals. The proper destination for these one-hot signals is the Chip Enable input of each memory IC. When a bank’s CE is asserted, it responds to the common address/data and WE/OE signals; all other banks remain disabled (outputs high-impedance), preventing bus contention. Step-by-Step Solution: 1) Choose the number of banks N; a log2(N)-to-N decoder uses the top address bits to generate N select lines.2) Connect each decoder output to the CE of one memory IC.3) Tie all address lines (remaining bits) and the data bus in parallel across ICs.4) Fan out common control signals WE/OE to all ICs; only the enabled CE bank drives or stores data. Verification / Alternative check: Timing diagrams and bus truth tables show that with CE inactive, a device ignores reads/writes and tri-states outputs, proving CE is the correct selection pin for decoder outputs. Why Other Options Are Wrong: Most significant address inputs are data selectors, not bank selects. Data inputs carry payload, not selection. The read/write line defines operation type, not which chip is active. Common Pitfalls: Driving OE instead of CE (can still cause partial activation); leaving disabled chips with outputs enabled; forgetting to buffer signals when fan-out is large. Final Answer: The chip enable

Question 9

Mask ROM characteristics: Complete the statement—Information stored in a mask ROM is programmed during manufacturing and its contents are fixed thereafter. Which option best describes this behavior?

Accepted Answer

Introduction / Context: Read-Only Memory (ROM) technologies vary by how data is placed into the device and whether it can be altered later. Mask ROM is the oldest and densest fixed ROM type: its bit patterns are defined during wafer fabrication using custom masks. Understanding mask ROM helps differentiate it from PROM, EPROM, and EEPROM in terms of flexibility and use cases. Given Data / Assumptions: Technology: Mask ROM with patterns set in silicon at manufacture. No field programmability is available after fabrication. Nonvolatile behavior: data persists without power. Concept / Approach: Because data is encoded physically by diffusion/metal layers, mask ROM cannot be altered after production. This yields low cost per bit at high volumes but requires long lead times and firm data maturity. Devices such as PROM/EPROM/EEPROM provide post-fab programming or erasure methods and are chosen when data may change or volumes are lower. Step-by-Step Solution: 1) Identify mask ROM: data defined by masks in the fab process.2) Recognize nonvolatile retention: no refresh or power required to keep data.3) Conclude that field modifications are impossible.4) Therefore, the accurate description is that the manufacturer stores the data and it cannot be changed. Verification / Alternative check: Device datasheets and manufacturing flows for mask ROM emphasize one-time definition and no reprogramming capability, unlike PROMs and E(E)PROMs. Why Other Options Are Wrong: “Can be modified” applies to field-programmable devices, not mask ROM. “Is lost if power is interrupted” confuses ROM with volatile RAM. Combining those two errors remains incorrect. Common Pitfalls: Equating any ROM with rewritable flash; assuming nonvolatile implies reprogrammable. Final Answer: is stored by the manufacturer and cannot be changed

Question 10

ROM timing definition: What is meant by ROM access time in datasheets? Choose the option that correctly defines the interval from a valid address being applied to valid output data appearing at the device pins.

Accepted Answer

Introduction / Context: Access time is a key specification for read-only memories and other asynchronous memories. It informs system designers how quickly a CPU or controller can read stable data given address setup and control signals, impacting clock frequency, wait states, and bus timing margins. Given Data / Assumptions: Asynchronous ROM with address, chip enable, and output enable signals. Access time measured to valid logic levels at data outputs. Programming time is unrelated to read access performance. Concept / Approach: Access time is defined as the interval between a defined starting condition—typically address valid with chip enabled—and the moment when output data is guaranteed valid. ROMs are read-only in operation; “write time” is irrelevant in normal use. Precise timing paths (tAA, tCE, tOE) may be specified, but the common description aligns with option (c). Step-by-Step Solution: 1) Apply a valid address while asserting CE and possibly OE.2) Internal decoding and sensing occur.3) After the specified interval (access time), outputs settle to valid levels.4) System can sample data safely after this time or when a ready/hold-off signal indicates readiness. Verification / Alternative check: Open any ROM/flash datasheet and observe tACC or related parameters defined exactly as address-to-data-valid intervals. Why Other Options Are Wrong: Programming time is for EPROM/EEPROM write operations, not ROM access. There is no meaningful “difference between READ and WRITE times” for ROM. Address activation wording in (d) is not the standard definition. Common Pitfalls: Misinterpreting OE gating delays as access time alone; ignoring that multiple timing paths can qualify data validity. Final Answer: the time it takes to get valid output data after a valid address is applied

Question 11

Dynamic memory behavior: Select the best definition—Dynamic memory (DRAM) is memory ________.

Accepted Answer

Introduction / Context: Dynamic Random-Access Memory (DRAM) dominates main memory because it offers very high density at low cost per bit. Its defining characteristic is the need for periodic refresh due to charge leakage in its storage capacitors. Comparing DRAM with SRAM clarifies why refresh is necessary and how controllers manage it transparently to the CPU. Given Data / Assumptions: DRAM cell: 1 transistor + 1 capacitor stores charge for a bit. Leakage currents discharge the capacitor over time. External or integrated controllers perform refresh cycles regularly. Concept / Approach: Because stored charge decays, DRAM must be rewritten (refreshed) within a specified retention interval (e.g., every 64 ms or less depending on device). During refresh, rows are read and rewritten to restore charge. In contrast, SRAM uses cross-coupled inverters that hold state as long as power is present, without refresh, though it remains volatile. Step-by-Step Solution: 1) Recognize DRAM cell structure and leakage.2) Use a refresh controller to cycle through all rows within the retention time.3) Memory remains coherent to the CPU because refresh is interleaved with normal accesses.4) Therefore, the accurate definition is that DRAM requires periodic refresh. Verification / Alternative check: Memory controller datasheets specify refresh rates (e.g., tREFI) and timing parameters (tRFC), confirming periodic refresh requirements. Why Other Options Are Wrong: Maintaining storage without power is nonvolatile behavior, not DRAM. “Data can never be altered” contradicts the writeable nature of RAM. “Maintains storage as long as power is applied” fits SRAM more closely but omits DRAM’s refresh need. Common Pitfalls: Thinking DRAM is nonvolatile; overlooking the performance impact of refresh on tight latency budgets. Final Answer: that must be refreshed periodically or it will lose storage

Question 12

PROM programming mechanism: Programmable Read-Only Memories (PROMs) are one-time programmable devices. They are programmed by permanently altering on-chip fuses. Choose the most accurate verb describing this fuse action.

Accepted Answer

Introduction / Context: PROM devices allow a user or manufacturer to program fixed data patterns after fabrication but only once. The programming process uses elevated voltages and currents to permanently change the state of fusible links, defining 1s and 0s in the array. Understanding the correct terminology clarifies how PROMs differ from erasable types like EPROM and EEPROM. Given Data / Assumptions: PROMs contain fusible links or antifuses per memory cell. Programming is irreversible in standard PROMs. Terminology often used in datasheets: “blow the fuses.” Concept / Approach: During programming, a controlled overcurrent melts (opens) a fusible link, or closes an antifuse structure, setting the logical state. This permanent change is succinctly described as “blowing” fuses. Other terms like “charging” fit EPROM/EEPROM mechanisms (charge storage in floating gates), not fuse-based PROMs. Step-by-Step Solution: 1) Apply programming voltage per device spec.2) Drive programming current through selected links.3) Physical change in the fuse sets the bit permanently.4) Verify programmed pattern; no erasure step exists for standard PROM. Verification / Alternative check: PROM datasheets and historical references describe one-time programmability via fuses/antifuses and use the verb “blow” for fuses. Why Other Options Are Wrong: “Zapping” is colloquial and non-specific. “Charging” implies floating-gate devices (EPROM/EEPROM/flash). “Inputting” is not a physical mechanism. Common Pitfalls: Confusing PROM with EPROM/EEPROM; assuming programmed PROM can be erased. Final Answer: blowing

Question 13

DRAM maintenance term: The periodic recharging of dynamic RAM memory cells—performed to restore charge on the storage capacitors—is called ________.

Accepted Answer

Introduction / Context: Dynamic RAM cells store information as charge on tiny capacitors that leak over time. To prevent data loss, the memory controller periodically re-reads and rewrites each row, restoring the charge. The formal term for this operation is “refresh.” Given Data / Assumptions: DRAM cells are 1T1C: one access transistor and one capacitor. Charge leakage necessitates periodic maintenance. Refresh can be distributed or burst, transparent to the CPU. Concept / Approach: Refreshing cycles through all rows within a specified retention time. Each refresh activates a row, the sense amplifiers restore the original levels, and the data is preserved. Standards define timing parameters (e.g., tREFI, tRFC) to ensure integrity. Step-by-Step Solution: 1) Controller issues a refresh command for a specific row or set of rows.2) The row is sensed; contents are restored to full logic levels.3) Repeat so that every row is refreshed within the retention window.4) Normal read/write cycles are interleaved around refresh operations. Verification / Alternative check: JEDEC standards and DRAM datasheets specify refresh cycles and effects on bus availability, confirming the terminology. Why Other Options Are Wrong: “Reinstalling,” “revitalizing,” and “reinstating” are not standard technical terms in DRAM documentation. Common Pitfalls: Assuming refresh can be skipped; not budgeting timing for refresh-induced pauses in tight real-time systems. Final Answer: refreshing

Question 14

Nonvolatile, electrically erasable memory type: Select the device that is user programmable and can be erased electronically and reprogrammed many times without removal from the circuit.

Accepted Answer

Introduction / Context: Nonvolatile memories differ in how they are programmed and erased. Choosing the right technology depends on update frequency, in-circuit programmability, endurance, and data retention. The common technologies are PROM, EPROM, EEPROM, and flash (a variant of EEPROM array architectures). Given Data / Assumptions: PROM: one-time programmable via fuse/antifuse. EPROM: erasable with ultraviolet light; requires removal from circuit for exposure. EEPROM: electrically erasable and programmable in-circuit. Mask ROM: fixed at manufacture (not listed among options here but conceptually distinct from ROM generic). Concept / Approach: EEPROM supports electrical erasure at byte or small block granularity and reprogramming without removing the device. It is field-updatable and well-suited to configuration storage. PROM cannot be erased; EPROM requires UV light and typically a windowed package; generic ROM is not user-programmable. Step-by-Step Solution: 1) Eliminate non-rewritable options: PROM and plain ROM are not erasable by the user.2) Consider EPROM: rewritable but only via UV exposure, not electronic in-circuit erasure.3) EEPROM matches the requirement: user programmable, electronically erasable, reprogrammable many times.4) Therefore select EEPROM. Verification / Alternative check: Device families and microcontroller datasheets (e.g., on-chip EEPROM) explicitly state electronic erase/program capability and endurance ratings in write cycles. Why Other Options Are Wrong: PROM is one-time programmable. ROM is manufactured with fixed contents. EPROM requires UV light and removal from circuit for erasure. Common Pitfalls: Confusing flash and EEPROM granularity; assuming EPROM can be erased electrically—it cannot. Final Answer: EEPROM

Question 15

Address bit calculation: Because 4096 = 2^12, determine how many address bits are required for a 4K × 1 RAM to uniquely address all storage locations.

Accepted Answer

Introduction / Context: Address lines select unique memory locations. The number of address bits determines the maximum addressable depth according to a power-of-two relationship. Designers must compute this quickly when planning memory maps and decoding logic. Given Data / Assumptions: Total locations: 4K = 4096 addresses. Each address selects one 1-bit cell (width is irrelevant to address count). Binary addressing: N address lines can select 2^N unique locations. Concept / Approach: Find N such that 2^N = 4096. Recognize that 4096 is 2^12. Therefore N = 12 address bits are required, commonly labeled A0 through A11. This is independent of the data width; a 4K × 8 device also uses 12 address lines for the same depth. Step-by-Step Solution: 1) Note 4K = 4096 = 2^12.2) Use formula: number_of_locations = 2^N → solve for N = log2(4096) = 12.3) Thus 12 address inputs are needed to uniquely select each location.4) Labeling convention: A0 is LSB, A11 is MSB for 4K depth. Verification / Alternative check: Build a quick table: 2^10 = 1024, 2^11 = 2048, 2^12 = 4096; confirms 12 lines. Why Other Options Are Wrong: “4096” confuses count with number of address lines. “10” and “1024” correspond to 1K. Only 12 maps to 4096 addresses. Common Pitfalls: Mixing decimal K (1000) with binary K (1024); forgetting that width does not change address line count. Final Answer: 12

Question 16

ROM integrity testing technique: The checksum method is commonly used to test which type of memory by summing stored bytes/words and comparing against a known expected value?

Accepted Answer

Introduction / Context: Checksums provide a simple, fast method to verify data integrity by reducing a block of data to a short signature. In embedded systems and firmware distribution, checksums (or stronger hashes) are frequently used to validate code stored in nonvolatile memory before execution, ensuring no corruption during manufacturing or field updates. Given Data / Assumptions: Memory under test contains relatively static contents (e.g., firmware or lookup tables). A known expected checksum is available from a trusted build process. Test computes a runtime checksum and compares it to the stored or expected value. Concept / Approach: ROM (including EPROM/flash used as ROM) typically stores fixed code and data that should not change spontaneously. A checksum over its contents detects bit flips or programming errors. While RAM can be tested with patterns (e.g., walking ones/zeros, March tests), RAM uses dynamic tests rather than a static checksum because its contents vary during operation. FPLAs are logic arrays, not byte-addressable memories suited to checksum-based validation. Step-by-Step Solution: 1) Compute checksum at build time and record it (e.g., store in a reserved location or externally).2) At power-on, read ROM contents and compute checksum using the same algorithm.3) Compare computed checksum to expected value.4) If they match, ROM contents are assumed valid; otherwise, signal error or fallback to recovery. Verification / Alternative check: Bootloaders and safety-critical systems commonly implement CRCs (a stronger form of checksum) over ROM images; manufacturing test also relies on checksums to verify programmed devices. Why Other Options Are Wrong: EEPROM can be checked similarly when used as ROM, but the canonical application cited in fundamentals is ROM. FPLAs are not validated via data checksums. RAM contents change constantly; integrity tests for RAM are pattern-based, not fixed-image checksums. Common Pitfalls: Confusing checksum (simple sum) with CRC (polynomial-based); forgetting to exclude the checksum field itself from the sum or to include it in a complementary fashion. Final Answer: ROM

Question 17

MOS memories — Identify which types of read/write semiconductor memories are available in mainstream MOS technology.

Accepted Answer

Introduction / Context: The question probes whether common read/write semiconductor memories implemented in MOS (metal–oxide–semiconductor) technology include static RAM (SRAM), dynamic RAM (DRAM), or both. Understanding this classification helps learners distinguish volatile, high-speed cache memories from high-density main memories, while connecting each to its underlying device physics and circuit techniques. Given Data / Assumptions: We are considering standard MOS processes used for VLSI memory fabrication. “Read/write memory” means the contents can be both read and rewritten during normal operation. Focus is on volatile memories commonly paired with CPUs. Concept / Approach: SRAM stores each bit in a bistable MOS circuit (often a 6-transistor cell) that holds state as long as power is present, without refresh. DRAM stores each bit as charge on a tiny capacitor accessed through a MOS transistor, offering much higher density but requiring periodic refresh. Both are fabricated using MOS processes and support read and write operations at runtime, hence both qualify as MOS read/write memories. Step-by-Step Solution: Identify SRAM: MOS cross-coupled inverters (bistable), no refresh needed while powered, very fast access, lower density.Identify DRAM: MOS access transistor + capacitor, requires refresh, slower per access than SRAM but extremely dense and cost-effective.Determine scope: Both are MOS and both are read/write memories. Verification / Alternative check: Inspect processor memory hierarchies: on-chip caches (SRAM) and off-chip system memory (DRAM) are both MOS and both read/write. Why Other Options Are Wrong: SRAM: True but incomplete; DRAM also qualifies.DRAM: True but incomplete; SRAM also qualifies.none of the above: Incorrect; both are standard MOS read/write memories. Common Pitfalls: Equating “MOS” only with non-volatile types like EPROM/EEPROM/flash and forgetting volatile MOS RAMs.Assuming only one of SRAM or DRAM is MOS-based. Final Answer: both of the above

Question 18

Memory timing — The operation that stores data at the addressed location after presenting a new valid address is called what?

Accepted Answer

Introduction / Context: Digital systems interact with memory using well-defined bus timing. After a valid address is placed on the bus, the controller either reads the contents at that location or stores new data there. Correctly naming these operations is fundamental to interpreting datasheets and designing memory controllers. Given Data / Assumptions: “New address” means the address bus has been updated and stabilized. Separate control signals indicate read or write intent (e.g., /RD, /WR). We are discussing generic semiconductor memories (RAM, ROM, etc.). Concept / Approach: A write cycle is the sequence in which the controller asserts the write control, drives the data bus with the value to be stored, and meets setup/hold and pulse-width timing so the memory latches the new data into the addressed cell. In contrast, a read cycle retrieves data from the selected address, and a refresh cycle is specific to DRAM retention rather than user data storage. Chip select simply enables a device; it is not an operation by itself. Step-by-Step Solution: Apply address A on the bus and assert chip select to enable the target memory.Drive the data bus with the value D intended for storage.Assert write control for the required write pulse width; meet setup/hold times so the memory stores D at A. Verification / Alternative check: Check timing diagrams in RAM datasheets: “Write cycle timing” explicitly shows address setup, data valid window, and /WE pulse controlling storage. Why Other Options Are Wrong: a read cycle: Fetches data; does not store it.a refresh cycle: Maintains DRAM charge but does not accept external user data.chip select: An enabling signal, not a complete operation storing data. Common Pitfalls: Confusing enabling a device (chip select) with performing a write.Thinking “refresh” is a type of write; it is internal maintenance for DRAM integrity. Final Answer: a write cycle

Question 19

Terminology in context — When engineers say “RAM” in semiconductor memory discussions (contrasting with ROM), they usually mean what?

Accepted Answer

Introduction / Context: “RAM” can mean two different things depending on context: the broad theoretical definition “random access memory” (any memory with uniform access time) and the practical industry shorthand contrasting RAM with ROM. The question tests your familiarity with this practical usage in semiconductor memory discussions. Given Data / Assumptions: Context explicitly contrasts RAM with ROM (read-only memory). Audience is digital designers and computer engineers. We focus on common industry parlance rather than strict textbook definitions. Concept / Approach: In practice, when engineers informally say “RAM” versus “ROM,” they are usually distinguishing memories that can be written during normal system operation from those that cannot. Thus “RAM” in this contrast means read/write memory (RWM), such as SRAM and DRAM. While “random access” is the full expansion of the acronym, the intended practical distinction in this specific phrasing is writability at runtime, not just addressability pattern. Step-by-Step Solution: Recognize the comparison frame: RAM vs ROM implies writability.Map “RAM” in that frame to read/write memory used for working data (SRAM/DRAM).Conclude that the best answer is “Read/Write Memory (RWM).” Verification / Alternative check: Observe datasheets and textbooks: “RAM (read/write)” versus “ROM (read-only)” is a standard explanatory pairing. Why Other Options Are Wrong: Random-Access Memory: Literal expansion, but the question asks about usage “as opposed to ROM,” which emphasizes writability.flash memory: A specific non-volatile technology; not what “RAM” usually refers to here.temporary storage: Colloquial, not a precise technical meaning for this comparison. Common Pitfalls: Taking acronyms only literally and missing the conversational technical intent.Assuming “temporary” equals “RAM” without considering write capability and volatility. Final Answer: Read/Write Memory (RWM)

Question 20

DRAM addressing — Why do DRAM chips include separate RAS (Row Address Strobe) and CAS (Column Address Strobe) signals?

Accepted Answer

Introduction / Context: Dynamic RAMs (DRAMs) achieve very high density per package. One key technique is address multiplexing: using the same physical address pins for both row and column addresses at different times. This requires explicit control strobes to tell the chip when to latch each half of the address. Understanding RAS and CAS clarifies DRAM timing and controller design. Given Data / Assumptions: DRAM core is organized as a 2-D array indexed by row and column. Pin count is constrained by package cost/size. Timing is managed by external memory controllers asserting RAS/CAS. Concept / Approach: To minimize pins, DRAMs present a multiplexed address bus: first the controller drives the row portion and asserts RAS to latch it; then it drives the column portion and asserts CAS to latch it. This splits the full address across time rather than pins, keeping packages compact while accessing any cell in the array. Step-by-Step Solution: Controller places RowAddr on address pins and asserts RAS → row is latched.Controller then places ColAddr on the same pins and asserts CAS → column is latched.The intersection cell is selected; read or write proceeds. Verification / Alternative check: Examine JEDEC timing: RAS-before-CAS sequences and parameters (tRCD, tRAS) reflect the multiplexed addressing mechanism. Why Other Options Are Wrong: the RAS determines operation mode and the CAS enables tristate outputs: Misstates their roles; mode and bus tri-state are handled differently.the RAS latches in the address and the CAS latches in data: CAS latches column address; data transfer is governed by read/write timing, not CAS latching “data.”None of the above: Incorrect because option (a) correctly describes the reason. Common Pitfalls: Confusing CAS with data latch rather than column address latch.Ignoring that address multiplexing is primarily for pin-count reduction. Final Answer: the address lines are multiplexed to reduce pin count

Memory and Storage Questions