DRAM cell refresh — common refresh period For mainstream dynamic RAM (DRAM) devices, which of the following is the typical refresh period used to retain data stored on capacitive cells?

Introduction / Context:
DRAM stores each bit as charge on a tiny capacitor, which leaks over time. To prevent data loss, each row must be periodically refreshed (read and rewritten). Knowing the customary refresh period is essential for memory controller design and performance analysis.

Given Data / Assumptions:

• DRAM requires periodic refresh of all rows.
• Common period for legacy and many commodity parts is approximately 64 ms (some extended-temp parts require 32 ms).
• Refresh can be distributed across the interval to reduce performance impact.

Concept / Approach:
The refresh interval defines how often all rows must be accessed to maintain charge. Controllers schedule refresh commands such that every row is refreshed at least once during the specified 64 ms window, balancing data integrity and bandwidth.

Step-by-Step Solution:
Identify the standard window: 64 ms for typical operating temperatures.Map rows to refresh cycles: e.g., 8K rows → 8K refreshes per 64 ms.Controller issues periodic refresh at intervals (for 8K rows, ~7.8 µs between refreshes).

Verification / Alternative check:
JEDEC specifications and device datasheets list tREFI (refresh interval) such that all rows are refreshed within 64 ms under normal temperature ranges, confirming the common value.

Why Other Options Are Wrong:

• 2 µs / 64 µs: Far too frequent for full-array refresh; would waste bandwidth.
• 2 ms: Too short versus typical spec and not a standard whole-array interval.

Common Pitfalls:

• Confusing tREFI (interval between refresh commands) with the total 64 ms window.
• Not accounting for reduced refresh windows (e.g., 32 ms) at high temperature grades.

Final Answer:
64 ms