Question 1

DRAM control signal convention During a DRAM read cycle, what is the correct logic level of the Read/Write (R/W or WE) control signal?

Accepted Answer

Introduction / Context: Dynamic RAMs (DRAMs) use control pins such as RAS, CAS, and a write-control pin (often labeled WE or R/W). Knowing the correct polarity of these signals for read versus write is essential when designing memory controllers or debugging bus transactions. Given Data / Assumptions: Typical DRAM write-enable pin (WE) is active-LOW for write. Read occurs when WE is deasserted (logic HIGH) while RAS/CAS perform row/column latching. Exact naming varies, but the polarity convention is consistent: LOW = write, HIGH = read. Concept / Approach: If the write-control input is LOW, the device performs a write when properly addressed. To read, the write function must be disabled, which is achieved by setting WE (or R/W) HIGH so the sense amps drive data out during the CAS phase. Step-by-Step Solution: Determine the meaning of WE/RW signal: LOW → write; HIGH → not writing.A read requires not-writing, therefore WE (or R/W) must be HIGH.Thus, during a read cycle the correct level is HIGH. Verification / Alternative check: Cross-check with standard DRAM timing diagrams: WE = 1 for read, WE = 0 for write, with RAS/CAS sequencing the row and column. Why Other Options Are Wrong: Low: would initiate write. Hi-Z: control inputs are driven logic signals, not tri-stated. None of the above: unnecessary since HIGH is correct. Common Pitfalls: Confusing signal labels (R/W vs WE). Always check active polarity in the datasheet; conventionally, read requires WE HIGH. Final Answer: High

Question 2

Electrically erasable ROM types Which ROM family can be erased by an electrical signal rather than by ultraviolet light or factory masks?

Accepted Answer

Introduction / Context: Nonvolatile memories differ in how stored data can be removed (erased) and rewritten. Understanding the erase mechanism is important for in-system reprogramming and product maintenance strategies. Given Data / Assumptions: Mask ROM is fixed at manufacture and cannot be erased. EPROM is erased with ultraviolet (UV) light through a quartz window. EEPROM (and Flash EEPROM) can be erased electrically. Concept / Approach: The question specifically asks for a ROM that can be erased using an electrical signal. This points directly to EEPROM technology, which supports byte- or block-level electrical erase and reprogramming, enabling in-circuit updates without special UV exposure. Step-by-Step Solution: Eliminate mask ROM (no erase) and EPROM (UV erase).Select EEPROM as electrically erasable/reprogrammable.Therefore, the correct answer is EEPROM. Verification / Alternative check: Modern Flash memory is a derivative of EEPROM (electrically erasable) with block erase; classic EEPROMs support byte-level erase/write. Why Other Options Are Wrong: ROM: generic, often mask-programmed—no erasure. Mask ROM: fixed data, no erasure. EPROM: UV-light required for erasure, not purely electrical. Common Pitfalls: Assuming EPROMs can be erased electrically; they require UV unless explicitly Flash/EEPROM. Final Answer: EEPROM

Question 3

ROM verification by checksum — what does it tell you? When using the checksum method to test a ROM image, what information does a checksum failure actually provide?

Accepted Answer

Introduction / Context: Checksums and hashes are common techniques for verifying firmware integrity in ROM/Flash. A checksum provides a quick integrity check but conveys limited diagnostic information when it fails. Given Data / Assumptions: A checksum is typically a simple arithmetic or logical summary of all ROM bytes. A mismatch indicates at least one bit/byte differs from the expected image. No location-specific error correction information is inherent in a basic checksum. Concept / Approach: Because a checksum compresses the entire contents into a short value, many different error patterns can produce the same failure indication. Therefore, a failing checksum only signals that the image is not identical; it does not tell you where or how many bytes are wrong, nor does it correct them. Step-by-Step Solution: Compute checksum of ROM contents and compare with expected value.If mismatch → integrity failure detected.Conclusion: contents incorrect; no pinpointing or correction provided by the checksum itself. Verification / Alternative check: Contrast with error-correcting codes (ECC) or cryptographic hashes with chunking—those can help locate or correct errors; a simple checksum does not. Why Other Options Are Wrong: Options A and C imply location or count information—basic checksums do not provide this. Option B suggests correction capability, which requires ECC, not a simple checksum. Common Pitfalls: Over-relying on checksums for diagnostics; they are detection tools, not repair tools. Final Answer: simply indicates that the contents of the ROM are incorrect.

Question 4

In computer architecture, select the statement that best describes Read-Only Memory (ROM).

Accepted Answer

Introduction / Context: Read-Only Memory (ROM) is a fundamental concept in computer organization. It stores firmware and fixed data that must be preserved across power cycles, such as bootloaders or device configuration. This question checks whether you can distinguish ROM from volatile working memory like RAM. Given Data / Assumptions: ROM contents should remain preserved when power is removed. Typical usage includes firmware, microcode, and lookup tables. Contrast is with RAM, which loses its contents when power is removed. Concept / Approach: Nonvolatile memory retains stored bits without a continuous power supply. ROM is nonvolatile by definition and is used for data or instructions that are not expected to change during normal system operation. Although some ROM families are field-programmable or erasable (PROM, EPROM, EEPROM, Flash), during system runtime the stored code is not being continuously modified. Step-by-Step Solution: Identify the key property: nonvolatility.Identify typical role: stores static program code and constants.Eliminate choices that imply volatility or frequent operational updates.Select the description that states nonvolatile and unchanging during system operation. Verification / Alternative check: System block diagrams show ROM mapped for boot code. Power loss does not erase it, unlike RAM which needs refresh or loses state entirely. Why Other Options Are Wrong: Option A: Contradicts ROM usage; changing data belongs to RAM or nonvolatile rewritable memory under special procedures.Option C and D: Describe volatile memory behavior, not ROM.Option E: Battery-backed memory is a distinct category and still can be volatile if battery fails. Common Pitfalls: Confusing the ability to reprogram certain ROM types with normal operational changes. Reprogramming is a special maintenance action, not routine runtime behavior. Final Answer: Nonvolatile, used to store information that does not change during system operation

Question 5

In processor cache hierarchy terminology, L1 is known as which type of cache?

Accepted Answer

Introduction / Context: Modern CPUs use a hierarchy of on-chip caches to bridge the speed gap between processor cores and main memory. L1, L2, and L3 are common levels. This question asks you to correctly identify how L1 is referred to in that hierarchy. Given Data / Assumptions: L1 sits closest to the CPU core. Cache is implemented using SRAM cells, not DRAM. Naming reflects proximity and latency. Concept / Approach: L1 cache is the first-level cache with the lowest latency and highest bandwidth to the core. It is commonly called the primary cache. L2 is the secondary cache, and L3 is often a last-level shared cache. While physically implemented using SRAM, the term sought by the question is the hierarchical role, not the circuit technology. Step-by-Step Solution: Identify the level closest to the core: L1.Map level to terminology: L1 → primary cache.Confirm that L2 → secondary; L3 → last-level in many designs. Verification / Alternative check: CPU documentation lists L1 I-cache and L1 D-cache as the primary caches serving instruction and data fetches with minimal latency. Why Other Options Are Wrong: Secondary cache: corresponds to L2, not L1.DRAM: caches use SRAM for speed; DRAM is for main memory.SRAM: true technology, but the question asks what L1 is known as in the hierarchy, which is primary cache.Tertiary cache: not applicable to L1. Common Pitfalls: Equating cache level names with memory technologies. Level names describe hierarchy position; SRAM vs. DRAM describes implementation technology. Final Answer: Primary cache

Question 6

Select the statement that best describes a fusible-link PROM (Programmable Read-Only Memory).

Accepted Answer

Introduction / Context: A fusible-link PROM is a classic nonvolatile memory in which stored bits are created by selectively blowing microscopic fuses. Understanding the programmability and permanence of this technology is important for legacy systems and fundamentals. Given Data / Assumptions: Programming is performed by the end user using a programmer device. Once a fuse is blown, the change is permanent. No built-in erase mechanism exists for fusible-link PROMs. Concept / Approach: Fusible-link PROMs start with all links intact and represent one logical state. Programming selectively opens links by a controlled current pulse, changing those cells to the opposite state. Because there is no way to restore a blown fuse, these devices are one-time programmable at the user level. Step-by-Step Solution: Identify technology mechanism: physical fuse links.Determine programmability: performed by user with a PROM programmer.Assess reversibility: irreversible, hence one-time programmable.Select the description that matches these facts. Verification / Alternative check: Device datasheets and textbooks explicitly call fusible-link PROMs OTP (one-time programmable) memories programmed by the user after manufacturing. Why Other Options Are Wrong: Manufacturer-programmable: confusion with mask ROM, which is programmed during fabrication.Reprogrammable options: describe EPROM/EEPROM/Flash, not fusible-link PROM.UV erasable: that is EPROM with a quartz window, not fusible-link PROM. Common Pitfalls: Mixing up PROM with EPROM or mask ROM. PROM is user-programmable but not erasable; mask ROM is factory programmed; EPROM is UV erasable; EEPROM/Flash are electrically erasable. Final Answer: User-programmable, one-time programmable

Question 7

Troubleshooting a suspected bad RAM: address and data inputs show pulses; control pins are inactive (held HIGH); outputs probed show Q0, Q2, Q3 dim (floating) and Q1 solid HIGH. What is the most likely fault?

Accepted Answer

Introduction / Context: When a static RAM is not enabled (chip-select or output-enable held inactive HIGH), its data outputs enter a high-impedance state. A logic probe often shows a dim or indeterminate indication for Hi-Z lines. A single output that reads a strong logic HIGH under these conditions indicates a fault. This question tests your understanding of tri-stated outputs and failure signatures. Given Data / Assumptions: All address lines and data inputs are active, showing pulses. An active-low enable line (for example, OE or CE) is HIGH, so outputs should be disabled (Hi-Z). Probe readings: Q0, Q2, Q3 dim; Q1 solid HIGH. Concept / Approach: With outputs disabled, every data output should float. A logic probe typically shows a weak or dim indication on a floating node due to leakage or capacitive pickup. A single pin stuck at a solid HIGH while disabled suggests a short or internal latch-up to Vcc on that specific output driver. Step-by-Step Solution: Outputs should be Hi-Z when the active-low control is HIGH.Dim indications on Q0, Q2, Q3 are consistent with Hi-Z.Q1 showing a solid HIGH contradicts Hi-Z behavior.Therefore, Q1 is likely shorted to Vcc internally; the chip should be replaced. Verification / Alternative check: Power down, measure resistance from Q1 to Vcc. If abnormally low, the pin or driver is shorted. Also confirm behavior persists with the IC removed from the circuit to rule out board-level shorts. Why Other Options Are Wrong: Option A and D: Multiple open outputs would not present as a solid HIGH on Q1.Option C: Only partly explains dim outputs, not the strong HIGH on Q1.Option E: Observation does not match a ground short. Common Pitfalls: Misreading logic probe brightness and forgetting that disabled outputs are tri-stated, not driven. A single driven level while disabled is a strong indicator of a fault on that pin. Final Answer: Q1 output is shorted to Vcc; replace the chip

Question 8

What is a major disadvantage of Random Access Memory (RAM) compared with nonvolatile memory?

Accepted Answer

Introduction / Context: RAM is indispensable for fast, temporary data storage, but it has a key drawback compared to ROM, Flash, and other nonvolatile memories. Identifying this drawback is important in system design decisions, especially for data retention and boot strategies. Given Data / Assumptions: RAM includes DRAM and SRAM categories. Nonvolatile memories retain data without continuous power. Speed is not the issue; RAM is faster than secondary storage. Concept / Approach: The defining limitation of RAM is volatility. When power is removed or drops below retention levels, the stored information disappears. DRAM also needs periodic refresh even while powered. Therefore, systems must reload working data and programs at power-up from nonvolatile storage. Step-by-Step Solution: Compare RAM to nonvolatile memory in terms of retention.Recognize that speed is a strength, not a weakness of RAM.Identify volatility as the major disadvantage that impacts persistence.Select the option that matches this core limitation. Verification / Alternative check: All computing platforms reload operating systems and applications into RAM at boot because RAM does not retain contents across power cycles. Why Other Options Are Wrong: Option A: RAM is fast; speed is not the disadvantage.Option B: Matrix size depends on design; not a general disadvantage.Option D: Power varies by type; not the principal drawback.Option E: RAM specifically supports random addressing; that is its advantage. Common Pitfalls: Confusing RAM's need for refresh (DRAM) with nonvolatility. Even SRAM loses data without power, so the core issue is volatility across all RAM types. Final Answer: It is volatile (data is lost when power is removed)

Question 9

In memory terminology, what does the phrase random access mean?

Accepted Answer

Introduction / Context: Random Access Memory is named for its ability to fetch any memory location directly and quickly, unlike sequential media. Understanding this definition helps differentiate RAM from devices such as tapes and certain serial memories. Given Data / Assumptions: We refer to electronic RAM devices (DRAM, SRAM). Access time is nominally independent of address location. Contrast with sequential access media. Concept / Approach: Random access means the device allows direct addressing of any location with roughly uniform access latency, regardless of the address chosen. This is distinct from block-based or seek-based devices where location strongly affects access time. Step-by-Step Solution: Define random access: direct, order-independent addressing.Contrast with sequential: must pass through preceding data to reach a target.Select the choice that states order independence and uniform timing. Verification / Alternative check: DRAM timing parameters do not depend on linear position in an address stream; although bank/row effects exist, the concept remains direct access compared with sequential media. Why Other Options Are Wrong: Option A and C: Describe sequential or indexed scanning, not random access.Option D: Describes mechanical seek latency for disks, not RAM.Option E: Some systems use paging, but RAM still supports direct addressing at word granularity. Common Pitfalls: Assuming block constraints of virtual memory paging limit RAM's access model. Paging is a system abstraction, not a property of the RAM device. Final Answer: Any address can be accessed in any order with equal access time

Question 10

In RAM testing, which fault types does the checkerboard pattern help detect?

Accepted Answer

Introduction / Context: The checkerboard test is a classic RAM diagnostic where alternating 0 and 1 values are written across memory cells, then inverted and verified. It is especially effective for catching coupling and adjacency-related defects. Recognizing what it detects helps in selecting appropriate test suites for memory validation. Given Data / Assumptions: Pattern 1010… and its inverse 0101… are written alternately. Cells that neighbor each other experience opposite states. Verification reads check for corruption after writes and inversions. Concept / Approach: By placing opposite logic values in adjacent cells, the checkerboard stresses leakage paths, shorts, and capacitive coupling. Inverting the pattern and rechecking validates that each cell can reliably store both states and is not influenced by neighbors beyond acceptable limits. Step-by-Step Solution: Write initial checkerboard: 1010… pattern to the entire region.Read back to confirm integrity; note any adjacent corruption.Write inverse pattern: 0101… across the same addresses.Read back again to confirm that each cell can hold the opposite state. Verification / Alternative check: Industry memory test suites (e.g., March algorithms) include checkerboard-like phases for adjacent-cell stress to catch interference and shorts efficiently. Why Other Options Are Wrong: Options A, B, and C individually describe specific fault classes; the checkerboard can address all of them collectively.Option E: Data bus faults need different tests like walking ones and zeros. Common Pitfalls: Assuming a single pass is sufficient. Both the pattern and its inverse must be tested to confirm bi-stability and neighbor independence. Final Answer: All of the above

Question 11

Select the statement that best describes volatile memory in computer systems.

Accepted Answer

Introduction / Context: Volatility is a key classification for memory devices and determines whether data persists across power cycles. This question checks foundational knowledge that separates RAM from nonvolatile technologies such as ROM, Flash, and magnetic storage. Given Data / Assumptions: Volatile memory requires continuous power to retain data. Typical volatile devices: DRAM, SRAM. Nonvolatile devices retain data without power. Concept / Approach: Volatile memory loses its contents when power is removed or drops below the retention threshold. This characteristic dictates system procedures for booting and state persistence, requiring that important data be saved to nonvolatile storage before shutdown. Step-by-Step Solution: Define volatile memory: data retention tied to power.Match this to the option that explicitly states loss of information without power.Reject options that confuse technology type with volatility. Verification / Alternative check: Everyday experience: PCs must reload the operating system into RAM at power-on. RAM contents vanish at power-off, confirming volatility. Why Other Options Are Wrong: Option A: Describes nonvolatile behavior.Options C and D: Magnetic or nonmagnetic says nothing about volatility.Option E: Some designs mitigate glitches but do not make volatile devices nonvolatile. Common Pitfalls: Assuming battery backup converts volatile memory into fundamentally nonvolatile memory. It only provides temporary retention while the battery lasts. Final Answer: Memory that loses stored information when electrical power is removed

Question 12

In DRAM systems, the periodic recharging of memory cell capacitors is called what?

Accepted Answer

Introduction / Context: Dynamic RAM stores data as charge on tiny capacitors that leak over time. To preserve data integrity, each row must be periodically accessed to restore the lost charge. This maintenance action has a standard name in memory design. Given Data / Assumptions: We are discussing DRAM, not SRAM. Cells leak charge and require periodic maintenance within a specified interval. System memory controllers schedule maintenance cycles. Concept / Approach: Refreshing is the act of reading a DRAM row and writing it back to restore charge. Memory controllers issue refresh commands automatically at intervals (for example, all rows within 64 ms). The process is transparent to software but affects available bandwidth. Step-by-Step Solution: Identify the storage mechanism (capacitive) and leakage problem.Define the maintenance operation: read and restore charge to the cells.Select the standard term used in datasheets and controller documentation: refreshing. Verification / Alternative check: DRAM timing specifications define refresh rates and retention times. Memory controllers expose settings such as refresh interval and count to guarantee data integrity. Why Other Options Are Wrong: Multiplexing: relates to sharing lines (e.g., address bus), not charge restoration.Bootstrapping and flashing: unrelated; flashing refers to Flash memory erase/program.Parity rewriting: an error-detection feature, not routine DRAM maintenance. Common Pitfalls: Confusing DRAM refresh with Flash memory operations. DRAM refresh is periodic and mandatory; Flash erase/program are infrequent maintenance or update operations. Final Answer: Refreshing

Question 13

Which statement best describes EPROM (Erasable Programmable Read-Only Memory) devices?

Accepted Answer

Introduction / Context: EPROM is a nonvolatile memory technology that can be erased and reprogrammed, but it requires a special erasure process. Identifying the correct erasure method helps distinguish EPROM from PROM, EEPROM, and Flash memory. Given Data / Assumptions: EPROM packages often include a quartz window. Erasure requires exposure to ultraviolet light of the proper wavelength and duration. After erasure, the device can be reprogrammed electrically. Concept / Approach: Unlike OTP PROM, EPROM is erasable. The stored charge on floating gates is neutralized by UV exposure through the window, returning cells to the erased state. Shorting inputs to ground does nothing to remove the stored charge on the floating gates. Step-by-Step Solution: Identify that EPROM is erasable and reprogrammable.Select the method: ultraviolet light exposure erases contents.Reject statements implying one-time programming or electrical shorting erasure. Verification / Alternative check: EPROM datasheets specify UV wavelength (often 253.7 nm) and exposure times for complete erasure and include handling precautions to prevent accidental UV exposure. Why Other Options Are Wrong: Option A: Describes PROM (one-time programmable), not EPROM.Option C: Shorting inputs does not erase floating-gate charge.Option D: Cannot be correct because A and C are incorrect.Option E: Nonvolatile memory does not self-erase on power loss. Common Pitfalls: Confusing EPROM with EEPROM or Flash, which are electrically erasable. EPROM specifically requires UV exposure to erase. Final Answer: EPROMs can be erased by ultraviolet light

Question 14

Fundamentals of digital information units In computer architecture and digital electronics, what is the smallest unit of binary data called?

Accepted Answer

Introduction / Context: Understanding how digital information is measured is foundational for computer science, embedded systems, and networking. The smallest unit identifies how data is stored, addressed, and manipulated at the hardware level. Given Data / Assumptions: The question asks for the smallest unit of binary data. Binary systems use two states: 0 and 1. Larger units (nibble, byte, word) are formed by grouping smaller ones. Concept / Approach: A single binary digit is the atomic piece of information in digital systems. Everything else—nibble (4 bits), byte (8 bits), word (platform-dependent, often 16/32/64 bits)—is composed of multiple such digits. Therefore, the smallest unit must be that single binary digit. Step-by-Step Solution: Identify the hierarchy: bit < nibble < byte < word.Recall definitions: bit = binary digit (0 or 1).Compare options and select the smallest unit by definition. Verification / Alternative check: Any digital storage specification (e.g., memory sizes, bus widths) ultimately breaks down to bit counts, confirming the bit as the smallest unit. Why Other Options Are Wrong: Nibble: equals 4 bits, not the smallest.Byte: equals 8 bits, not the smallest.Word: architecture-dependent and always multiple bytes/bits.BCD: a coding scheme, not a unit of size. Common Pitfalls: Confusing coding formats (like BCD) with size units; assuming a byte is always the smallest because it is commonly referenced in software. Final Answer: bit

Question 15

Memory addressing calculation How many address lines are required to uniquely address all locations in a 2K × 4 memory chip?

Accepted Answer

Introduction / Context: Determining the number of address lines needed for a given memory organization is a frequent task in digital design and microcontroller interfacing. Given Data / Assumptions: Memory size: 2K × 4 (2K addresses, 4 data bits per address). K uses the binary convention: 1K = 1024. Each unique address requires a unique binary code. Concept / Approach: If there are N addresses, the number of unique address codes required is N. The number of address lines A must satisfy 2^A ≥ N. For N = 2048, we solve 2^A = 2048. Step-by-Step Solution: Compute addresses: 2K = 2 × 1024 = 2048.Find A such that 2^A = 2048.Since 2^11 = 2048, A = 11 address lines. Verification / Alternative check: Confirm powers of two: 2^10 = 1024, 2^11 = 2048. Therefore, 11 is correct. Why Other Options Are Wrong: 8, 9, 10: 2^8, 2^9, 2^10 are 256, 512, 1024 addresses—insufficient.12: 2^12 = 4096 addresses—more than needed. Common Pitfalls: Confusing the data width (×4) with address lines; only the number of locations determines address line count. Final Answer: 11

Question 16

System start-up behavior Which type of memory is normally used to initialize a computer system’s hardware during power-on (bootstrapping)?

Accepted Answer

Introduction / Context: When a computer powers on, the CPU needs initial instructions before any operating system loads. This critical program is known as the bootstrap or firmware code. Given Data / Assumptions: The bootstrap code must be available immediately after reset. It cannot rely on disks or RAM being initialized. Nonvolatile storage is required to retain code without power. Concept / Approach: Bootstrap memory refers to ROM/flash that holds firmware such as BIOS or UEFI. The CPU vectors to fixed addresses in this memory to begin hardware initialization and system configuration. Step-by-Step Solution: At power-on: CPU fetches from a predefined reset vector.The vector maps to nonvolatile bootstrap memory.Firmware initializes hardware, memory controllers, and loads the OS loader. Verification / Alternative check: Motherboards contain a flash ROM chip storing BIOS/UEFI; embedded systems use on-chip ROM/flash for bootloaders. Why Other Options Are Wrong: Volatile memory (e.g., DRAM/SRAM) loses content when power is off; it cannot hold initial code.External mass memory (disk) is not directly executable at reset and needs initialized controllers.Static memory (SRAM) describes a technology, not specifically the boot memory role.Cache memory depends on valid backing store and is not the bootstrap source. Common Pitfalls: Equating “static memory” with nonvolatility; SRAM is still volatile. Final Answer: Bootstrap memory

Question 17

Memory-cell technology Which type of semiconductor memory uses a MOS capacitor as the storage element (one transistor plus capacitor per bit)?

Accepted Answer

Introduction / Context: Memory technologies differ by how each bit is stored. This affects density, speed, and controller complexity. Given Data / Assumptions: Looking for the memory that uses a MOS capacitor as the actual charge-storage device. Common types: SRAM, DRAM, ROM, FIFO, EEPROM. Concept / Approach: Dynamic RAM (DRAM) stores data as electric charge on a tiny capacitor controlled by a MOS transistor. Because the charge leaks over time, it must be refreshed periodically. SRAM uses cross-coupled inverters (latches) and does not require refresh while powered. Step-by-Step Solution: Identify the memory with capacitor-based cell: DRAM.Recall characteristic: requires refresh due to leakage.Select DRAM from the list. Verification / Alternative check: Standard texts and datasheets describe DRAM cells as 1T1C (one transistor, one capacitor). Why Other Options Are Wrong: SRAM: latch-based, multi-transistor cell.ROM: stored via mask/programmable elements, not a dynamic capacitor cell.FIFO: first-in, first-out buffer organization, not a specific cell technology.EEPROM: electrically alterable floating-gate technology, not dynamic capacitors. Common Pitfalls: Assuming “static” equals nonvolatile; SRAM is still volatile. Final Answer: DRAM

Question 18

Memory system sizing How many 2K × 8 ROM chips are required to construct a 16K × 8 memory system (same data width, larger address space)?

Accepted Answer

Introduction / Context: Designers often build larger memories by banking multiple identical ICs. The key is matching data width and scaling address space appropriately. Given Data / Assumptions: Each ROM chip: 2K × 8 (2048 addresses, 8-bit data). Target system: 16K × 8 (16384 addresses, 8-bit data). Same data width means chips are added in the address dimension, not in parallel for width. Concept / Approach: To expand from 2K to 16K at the same width, you need 16K / 2K chips in the address “stack.” The data width already matches at 8 bits, so you do not need to gang chips in parallel for width. Step-by-Step Solution: Compute: 16K / 2K = 8.Arrange 8 ROMs with chip-select decoding to cover all address ranges.Keep data buses in common and select one chip at a time. Verification / Alternative check: Total capacity check: 8 × (2K × 8) = 16K × 8, confirming the requirement. Why Other Options Are Wrong: 2, 4: provide only 4K × 8 or 8K × 8 respectively.16 or 32: would exceed the target size at constant width. Common Pitfalls: Combining chips to increase width unnecessarily; forgetting chip-select decoding. Final Answer: 8

Question 19

Storage devices – portability Which of the following is not a removable drive type commonly referenced in PC hardware?

Accepted Answer

Introduction / Context: Legacy and modern storage devices vary in whether media can be easily inserted or removed. Recognizing removable versus non-removable helps in system maintenance and data portability. Given Data / Assumptions: Zip, Jaz, and SuperDisk were removable-media drives popular in the 1990s–2000s. Hard drive here refers to a traditional internal HDD with fixed platters (non-removable by design at the user level). USB flash is removable, though not listed in the original set it is included as a plausible distractor context. Concept / Approach: Removable storage allows swapping media without opening the computer chassis. Internal HDDs are typically fixed inside the case; while the entire drive can be replaced, the data-bearing platters are not user-swappable media. Step-by-Step Solution: Identify removable-media products: Zip (Iomega), Jaz (Iomega), SuperDisk (LS-120).Recognize that a standard internal hard disk is not a removable-media drive.Select “Hard” as the non-removable option. Verification / Alternative check: Product literature describes Zip/Jaz/SuperDisk as cartridge-based removables; HDDs are installed inside the chassis and not used as swappable media. Why Other Options Are Wrong: Zip, Jaz, SuperDisk: explicitly removable cartridges/disks.USB flash: removable by nature. Common Pitfalls: Confusing “external USB hard drives” with removable-media drives; the enclosure is removable, but the storage medium is not a swappable cartridge. Final Answer: Hard

Question 20

Bit capacity calculation from organization A memory has 2048 addressable locations, each storing 8 bits. What is the total capacity of this memory in bits?

Accepted Answer

Introduction / Context: Translating between addresses, data width, and total capacity is a core skill when sizing memories in digital systems. Given Data / Assumptions: Total addresses = 2048 (which equals 2^11). Data per address = 8 bits. We are asked for total capacity in bits (not bytes). Concept / Approach: Total capacity (in bits) = number of addresses * bits per address. No conversion to bytes is needed since the answer is requested in bits. Step-by-Step Solution: Compute: 2048 * 8 = 16384 bits.Note that 16384 bits = 2^14 bits.Therefore, the correct capacity is 16384 bits. Verification / Alternative check: As a cross-check, convert to bytes: 16384 bits / 8 = 2048 bytes = 2 KB, which is consistent with 2048 addresses of 1 byte each. Why Other Options Are Wrong: 4096 and 8192: too small; correspond to 2048 × 2 or 2048 × 4, not ×8.32768 and 65536: too large; represent 4 KB and 8 KB in bits, not the specified memory. Common Pitfalls: Mixing bits and bytes or using decimal “K” instead of binary powers of two. Final Answer: 16384

Memory and Storage Questions