Memory and Storage Questions

• Address decoding for dynamic memory chip control may also be used for:
• FIFO is formed by an arrangement of ________.
• The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:
• Which of the following best describes static memory devices?
• To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?
• For the given circuit, what is the bit length of the output data word?
• What part of a Flash memory architecture manages all chip functions?
• Which of the following is not a flash memory mode or operation?
• Advantage(s) of an EEPROM over an EPROM is/are:
• The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.
• Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a) and displays the waveforms shown in figure (b). The actual analyzer display shows all four data outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output lines show a LOW level output. What is wrong, if anything, with the circuit?
• Typically, how often is DRAM refreshed?
• Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?
• The reason the data outputs of most ROM ICs are tristate outputs is to:
• CCD stands for ________.
• The mask ROM is ________.
• Why do most dynamic RAMs use a multiplexed address bus?
• What is the major difference between SRAM and DRAM?
• Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.
• On a CD-ROM, ________ are raised areas representing a 1.