Key DRAM characteristic — refresh requirement Which statement is a fundamental characteristic of dynamic RAM (DRAM) devices?

Introduction / Context:
DRAM cells store bits as charge on tiny capacitors, which leak over time. System designers must account for this by scheduling refresh operations. Recognizing this requirement is central to memory controller design and timing closure.

Given Data / Assumptions:

• DRAM cells = 1 transistor + 1 capacitor per bit.
• Charge leakage necessitates periodic refresh of all rows.
• Refresh frequency is specified in datasheets (for example, all rows within 32–64 ms).

Concept / Approach:

Refreshing reads a row and immediately rewrites it, restoring the stored charge in each capacitor. This is independent of normal CPU access. Without refresh, data decays to an indeterminate state, causing errors.

Step-by-Step Solution:

Verification / Alternative check:

Comparing with SRAM: no refresh is required. With nonvolatile memories: no refresh under power loss, but different constraints (erase/write cycles).

Why Other Options Are Wrong:

• Constantly changing input: incorrect—input activity is unrelated to data retention.
• “Broader dynamic range”: not a standard memory term.
• “Simpler devices”: cell may be simple, but system requirements (refresh logic) are not the defining characteristic.

Common Pitfalls:

• Assuming normal read/write accesses by the CPU alone will adequately refresh the entire array; controllers must guarantee all rows are refreshed in time.

Final Answer:

DRAMs must be periodically refreshed in order to be able to retain data.