Question 1

Magnetic media specification One of the most important density specifications for magnetic media (such as disks or tapes) is the:

Accepted Answer

Introduction / Context: Magnetic storage performance and capacity are influenced by several parameters. Among density metrics, the number of tracks per inch (TPI) is a key measure of how tightly data is packed radially on media. Given Data / Assumptions: Focus is on a specification intrinsic to media density. Applies to magnetic disks and tape systems. Concept / Approach: TPI directly reflects radial recording density. Higher TPI means more tracks on the surface, increasing potential capacity. While other specs like data transfer rate and RPM affect performance, TPI is a core density metric. Step-by-Step Solution: List candidate parameters.Identify which measure represents areal density in one dimension: TPI.Select “tracks per inch” as the answer. Verification / Alternative check: Storage datasheets commonly list TPI (radial) and bits per inch (linear) to derive areal density. Why Other Options Are Wrong: Rotation speed and data transfer rate are performance metrics, not density measures.Polarity reversal rate and spindle torque are not standard capacity indicators. Common Pitfalls: Confusing throughput (MB/s) with capacity density; both matter but measure different aspects. Final Answer: tracks per inch

Question 2

Identifying UV-erasable EPROM packages How can ultraviolet (UV) erasable PROMs (EPROMs) be visually recognized on a board or in inventory?

Accepted Answer

Introduction / Context: EPROM devices can be erased by exposing the silicon die to ultraviolet light. This requires a special package that allows UV to reach the die surface. Given Data / Assumptions: EPROMs are typically in ceramic packages with a quartz or glass window. UV light passes through the window to erase stored charge on floating gates. Other programmable memories (OTP PROM) lack the window and cannot be UV-erased. Concept / Approach: The unmistakable identifier of a UV-erasable EPROM is the transparent window. Labels are often placed over the window to prevent accidental erasure. Step-by-Step Solution: Look for a ceramic package with a circular/rectangular window.Recognize that markings or dots are not universal indicators.Select the option describing the window. Verification / Alternative check: Manufacturer packaging guides and component photos show the characteristic quartz window on UV EPROMs. Why Other Options Are Wrong: Colored dots or part-number prefixes are not standardized indicators.“Not identifiable” is incorrect; the window is explicit.Colored plastic packages are not used for UV erasure. Common Pitfalls: Confusing UV-erasable EPROM with OTP (one-time programmable) EPROM; OTP has no window. Final Answer: There is a small window on the chip.

Question 3

DRAM refresh interval (legacy specification) What is the maximum time interval allowed before a dynamic RAM must be refreshed to avoid data loss (choose the typical legacy textbook value)?

Accepted Answer

Introduction / Context: Dynamic RAM (DRAM) stores data as charge on tiny capacitors that leak over time. A refresh cycle periodically restores charge to prevent data loss. Given Data / Assumptions: Question refers to a typical legacy value taught in basic electronics/logic courses. Older DRAM generations often cited a refresh window in the 2–8 ms range for the entire array. We are asked for the maximum allowable interval before refresh. Concept / Approach: If a range such as 2–8 ms is considered typical, the maximum of that range is 8 ms. Waiting longer than the specified maximum can allow charge to decay below reliable sensing thresholds. Step-by-Step Solution: Recall typical legacy range: a few milliseconds (often 2–8 ms).Select the highest limit among given options that matches this range.Choose 8 ms as the maximum allowable interval. Verification / Alternative check: Datasheets vary by generation and temperature. Later devices specify longer intervals (for example, 64 ms at nominal conditions), but the foundational teaching example commonly uses 8 ms as the maximum in the basic set. Why Other Options Are Wrong: 2 ms and 4 ms are within the typical range but are not the maximum.10 ms exceeds the often-cited maximum for early DRAMs and risks data loss.16 ms is not among the original choices for many basic examples and is too long for the referenced range. Common Pitfalls: Mixing modern DRAM refresh specs (e.g., 64 ms) with classic textbook values targeted by this question. Final Answer: 8 ms

Question 4

Memory technologies – identifying how dynamic RAM (DRAM) stores one bit In dynamic semiconductor memory (DRAM), a single data bit is stored as charge on which circuit element?

Accepted Answer

Introduction / Context: This item checks core memory-technology knowledge: how dynamic random-access memory (DRAM) represents a single binary bit. Understanding the storage element explains why DRAM needs periodic refresh and how it differs from static RAM (SRAM) and register flip-flops. Given Data / Assumptions: The device class is DRAM (dynamic RAM). We are considering the physical circuit element that retains a 0 or 1. Binary information is represented by the presence or absence of electric charge. Concept / Approach: In DRAM, each cell pairs a MOS access transistor with a tiny capacitor. A stored 1 corresponds to charge on the capacitor; a 0 corresponds to little or no charge. Because the charge leaks over time, DRAM must be refreshed periodically. This is fundamentally different from SRAM, which uses cross-coupled inverters (flip-flop like) to hold state as long as power is applied. Step-by-Step Solution: Identify the technology: DRAM uses charge storage, not latch feedback.Determine the element that stores charge: the capacitor is the storage device.Conclude that the correct answer is the capacitor. Verification / Alternative check: Any DRAM cell schematic shows a single transistor connected to a storage capacitor; refresh specifications in datasheets further confirm charge-based storage. Why Other Options Are Wrong: Diode: Not used as the storage element in DRAM cells. Resistor: Not the charge-holding component; resistors conduct but do not store charge like capacitors. Flip-flop: Flip-flops are used in SRAM/registers; DRAM does not use a bistable latch per bit. Common Pitfalls: Confusing DRAM with SRAM and assuming a latch stores the bit. Overlooking the need for refresh, which is a direct consequence of capacitor leakage. Final Answer: capacitor

Question 5

Digital delay elements – definition of a multitap delay line What best describes a multitap digital delay line implemented with basic logic and passive components?

Accepted Answer

Introduction / Context: Multitap delay lines are used to create multiple well-defined timing references in digital systems (edge shaping, pulse stretching, time-stamping). Knowing their structure helps when analyzing propagation delay and jitter. Given Data / Assumptions: The delay line is “digital” and “multitap.” We consider simple gate-level realizations using passives for timing. Taps provide intermediate delayed versions of the same signal. Concept / Approach: A common discrete implementation chains inverters, each separated by an RC network to create incremental delays. Each node (tap) outputs a progressively delayed replica. Inverters are preferred because they provide restoration, squaring, and predictable propagation; RC networks introduce the controlled time constant. RL versions are uncommon in basic CMOS/TTL design, and using NANDs is unnecessary unless adding gating logic. Step-by-Step Solution: Identify the simplest delay element: inverter + RC forms a gate-level delay.Replicate stages and expose intermediate nodes as “taps.”Therefore, the best description is inverters with RC between each. Verification / Alternative check: Timing chains in many app notes show cascaded inverters with RC shaping or controlled delay cells; ECL/CMOS ICs also implement internal variants of this concept. Why Other Options Are Wrong: Inverters with RL: RL is not typical for logic-level delay; inductors are bulky and less predictable on PCBs. NAND + RC / NAND + RL: A NAND is not required for pure delay; it adds logic functionality rather than simple timing. Common Pitfalls: Thinking any multi-gate chain is a “multitap” even without RC timing control. Assuming inductive elements are common in digital delay blocks; they are not. Final Answer: a series of inverter gates with RC circuits between each one

Question 6

Memory width expansion – composing an 8 k × 8 from 8 k × 1 devices How many separate 8 k × 1 RAM chips are required to build a memory with word capacity 8 k and word length 8 bits (i.e., 8 k × 8)?

Accepted Answer

Introduction / Context: Designers often widen memory data paths by placing multiple narrow RAM ICs in parallel. This question tests the principle of data width expansion without changing address depth. Given Data / Assumptions: Available IC: 8 k × 1 (8,192 addresses, 1 data bit each). Target memory: 8 k × 8 (8,192 addresses, 8 data bits each). All devices share the same address and control lines to maintain identical depth. Concept / Approach: To increase word length from 1 bit to 8 bits while keeping the same number of addresses, connect eight identical 8 k × 1 chips in parallel on A0..A12 and control pins. Each chip supplies one bit of the 8-bit data bus (D7..D0). Step-by-Step Solution: Depth required = 8 k; each chip provides 8 k → match.Width required = 8 bits; each chip contributes 1 bit.Number of chips = 8. Verification / Alternative check: A quick block diagram shows eight chips with common address and enable signals, outputs OR rather “wired” onto separate data lines forming an 8-bit bus. Why Other Options Are Wrong: Four / Two / One: Would result in 4, 2, or 1 data bits per word, not the required 8. Common Pitfalls: Confusing “depth increase” (cascading addresses) with “width increase” (parallel data lines). Final Answer: Eight

Question 7

Hard disk metrics – identifying non-parameters of performance Which of the following is not a recognized hard disk performance parameter?

Accepted Answer

Introduction / Context: Disk performance is commonly summarized by seek time, rotational latency, and overall access time, which together affect throughput and responsiveness. Recognizing the correct terminology avoids confusion when reading storage specifications. Given Data / Assumptions: We compare listed terms with standard HDD metrics. Traditional HDDs use moving heads and spinning platters. Concept / Approach: Seek time measures how long the head takes to move to the right track. Latency (rotational latency) is the waiting time for the sector to rotate under the head. Access time is the sum (seek + latency, sometimes plus controller overhead). “Break time” is not a recognized HDD performance metric. Step-by-Step Solution: List recognized parameters: seek, latency, access.Identify the imposter term: break time.Select “Break time” as not a performance parameter. Verification / Alternative check: Vendor datasheets and benchmarks always cite seek, rotational latency, and access time; “break time” does not appear as a formal metric. Why Other Options Are Wrong: Seek time: Standard metric. Latency period: Standard metric (rotational latency). Access time: Standard composite metric. Common Pitfalls: Confusing “throughput” (MB/s) with time-based metrics; both are important but distinct. Final Answer: Break time

Question 8

Storage media classification – identifying non-magnetic technologies Which of the following is not a magnetic storage device?

Accepted Answer

Introduction / Context: Digital storage technologies are often grouped by their recording physics: magnetic, optical, and solid-state. Knowing the differences helps when discussing durability, rewrite cycles, and performance. Given Data / Assumptions: We compare representative devices against the “magnetic” category. Optical media encode data via pits/lands and reflectivity changes. Concept / Approach: Magnetic disk (HDD) and magnetic tape store data by magnetizing domains. Magneto-optical (MO) uses a laser to heat spots while a magnetic field sets polarity—hybrid but fundamentally uses magnetization to write. A pure optical disk (CD/DVD) uses physical/reflective features without magnetic fields; thus it is not magnetic storage. Step-by-Step Solution: Identify which option lacks magnetic recording: optical disk.Confirm others rely on magnetization.Choose “Optical disk.” Verification / Alternative check: Technical descriptions of CDs/DVDs/Blu-ray emphasize pits, lands, and reflectivity changes, not magnetic domains. Why Other Options Are Wrong: Magnetic disk: Magnetic storage. Magnetic tape: Magnetic storage. Magneto-optical disk: Uses magnetic writing with optical assistance, therefore magnetic-based. Common Pitfalls: Confusing “optical” with “magneto-optical.” They are different categories. Final Answer: Optical disk

Question 9

Hard disk assembly – recognizing mechanical components Which of the following is not a component found inside a typical hard disk drive (HDD)?

Accepted Answer

Introduction / Context: HDDs are precision electromechanical devices. Knowing their internal parts helps interpret specifications and failure modes. Given Data / Assumptions: A conventional HDD contains rotating media and a head positioning system. We identify which item does not belong to an HDD bill of materials. Concept / Approach: The spindle rotates the platters. Read/write heads fly over the surface to access data. A valve is not a standard HDD component; while HDDs include a breather/filter, there is no mechanical valve in the data path or motion system. Step-by-Step Solution: List typical HDD parts: platters, spindle motor, actuator/heads, PCB.Spot the odd term: valve.Select “Valve” as the non-component. Verification / Alternative check: Teardowns and manufacturer diagrams show spindles, platters, arms/heads, voice-coil actuators—no valves. Why Other Options Are Wrong: Spindle: Core rotating element. Platter: Magnetic medium. Read/write head: Magnetic transducer. Common Pitfalls: Confusing the breather hole/filter with a valve; they are passive vents with filters. Final Answer: Valve

Question 10

Address bus sizing – 512 × 8 organization from 4096 total bits How many address lines are required for a 4096-bit memory organized as 512 words × 8 bits per word?

Accepted Answer

Introduction / Context: Address line count is a fundamental design decision when interfacing memories. It depends on the number of addressable words (depth), not the number of bits per word (width). Given Data / Assumptions: Total memory: 4096 bits. Organization: 512 × 8 → depth = 512 words, width = 8 bits. Each unique address selects one of the 512 words. Concept / Approach: The required number of address lines A satisfies 2^A = number of addressable words. Here, words = 512. Since 512 = 2^9, we need 9 binary address lines. Width (8 bits) determines data bus size, not address count. Step-by-Step Solution: Compute words: 4096 bits / 8 bits per word = 512 words.Find A: 2^A = 512 → A = 9.Therefore, 9 address lines are required. Verification / Alternative check: Recall powers of two: 2^8 = 256, 2^9 = 512. Hence A = 9 is minimal and sufficient. Why Other Options Are Wrong: 2, 4, 8: 2^2 = 4, 2^4 = 16, 2^8 = 256, all too small for 512 addresses. Common Pitfalls: Multiplying by width when sizing address lines; address count depends only on depth. Final Answer: 9

Question 11

A burst refresh and a normal memory operation of a DRAM can be interspersed.

Accepted Answer

False

Question 12

The address-decoding scheme for a 16K-byte EPROM memory system requires a 1-to-8-address decoder when 4K × 8 memory is used.

Accepted Answer

True

Question 13

Main computer memory is usually DRAM because of its high density and low cost; cache memory is usually SRAM because of its high speed.

Accepted Answer

True

Question 14

Testing and troubleshooting the decoding logic will not reveal problems with the memory chips and their connections to the CPU busses.

Accepted Answer

True

Question 15

Fusible-link PROMs are programmed by removing the desired fuse links using a microscope and tweezers.

Accepted Answer

False

Question 16

A ROM that allows the user to program data into the chip by permanently opening fusible links is the EPROM.

Accepted Answer

False

Question 17

A group of 6 bits is also known as 1 byte.

Accepted Answer

False

Question 18

RAMs must have a input, in addition to data in.

Accepted Answer

True

Question 19

RAM stands for Readily Accessible Memory.

Accepted Answer

False

Question 20

A typical RAM will read (place stored data on its outputs) whenever the Chip Select line is active and the Write Enable line is inactive.

Accepted Answer

True

Memory and Storage Questions