Driving multiple TTL loads from a bus — memory interface requirement Because CPUs and memory ICs are typically specified to drive only one standard TTL load, what must be added if several inputs are being driven from the same bus line?

Introduction / Context:
Fan-out is the number of standard logic inputs that one output can reliably drive. Many microprocessors and memory parts are rated for about one standard TTL load. When a bus must fan out to multiple destinations, signal integrity and timing can degrade unless additional drivers are used.

Given Data / Assumptions:

• One bus line must feed several inputs.
• Each load adds input capacitance and DC current draw.
• The original device has limited fan-out capability.

Concept / Approach:
Buffering interposes a high-drive stage with stronger output currents (IOH/IOL) and lower output impedance to maintain valid logic levels and edge rates. Bus transceivers or dedicated line drivers are standard solutions on address/data buses and control signals.

Step-by-Step Solution:
Assess fan-out requirement vs. device rating.If multiple loads exceed rating, insert a buffer/driver.Use proper direction control if bidirectional (transceiver).

Verification / Alternative check:
Datasheets specify VOL/VOH at given currents. If total load exceeds spec, VOH/VOL may violate thresholds; a buffer restores margins and preserves timing.

Why Other Options Are Wrong:

• Decoded: Address decoding selects which device responds; it does not increase drive strength.
• Addressed/Stored: Not relevant to electrical drive capability.

Common Pitfalls:

• Ignoring capacitive loading and long traces that slow edges and cause ringing.
• Assuming pull-ups alone fix drive issues; active buffering is often required.

Final Answer:
Buffered