Write-cycle timing — correct sequence for a memory write Which timing sequence correctly describes a synchronous write operation to memory?

Introduction / Context:
A memory write requires that the target address and the data to be written both meet setup and hold times around the write strobe (WR). Getting the order wrong can corrupt data or write to the wrong location. Understanding the canonical sequence is foundational for timing analysis and bus design.

Given Data / Assumptions:

• Signals: Address, Data, Write Enable (WE or /WR).
• Setup time: Address and Data must be stable prior to the active write edge or level.
• Hold time: Address and Data must remain stable briefly after the write event.

Concept / Approach:
The correct sequence is: present the address, present valid data, then assert the write control to store the data at that address. Finally, deassert the write control and release or change bus lines after hold-time requirements are met. A “read pulse” never stores data, so any option saying that is incorrect.

Step-by-Step Solution:
tSU(Address, Data) → Address and Data valid.Assert /WR (active level or edge) to latch data into memory.tH(Address, Data) → Maintain stability for hold time; then deassert /WR.

Verification / Alternative check:
SRAM/DRAM datasheets show timing diagrams where address/data precede the write strobe, ensuring the device captures the intended value at the intended location.

Why Other Options Are Wrong:

• Address then data then read pulse: read pulse does not write.
• Write pulse first: violates setup; may write garbage or to wrong address.
• Data then write then address: violates both address and data setup requirements.

Common Pitfalls:

• Ignoring bus turnaround times when switching from read to write cycles.
• Overlooking that some memories require chip enable and output enable states to be inactive during writes.

Final Answer:
Assert the address and place valid data on the data bus; then apply the active write pulse to store the data