Introduction / Context:
Register-to-register data movement is ubiquitous in CPUs, microcontrollers, and digital signal processors. There are two primary paradigms: serial shifting (bit-by-bit over multiple clock pulses) and parallel transfer (all bits simultaneously). Understanding the difference is essential for estimating latency and designing control logic.
Given Data / Assumptions:
- Two distinct register banks are involved (source and destination).
- “Parallel transfer” means all N bits move concurrently across N data lines.
- Standard synchronous control signals like LOAD, ENABLE, or WRITE are available.
Concept / Approach:
In a parallel transfer, data lines carry all bits at once; the destination register captures them in a single action (often one clock, strobe, or load pulse). Shift pulses are associated with serial transfers, where each shift moves data by one position and multiple pulses are needed to move a full word.
Step-by-Step Solution:
Define serial vs. parallel: serial uses a single data line with shifting; parallel uses multiple lines simultaneously.Evaluate the claim: “Parallel transfer requires more than one shift pulse.”Recognize that shifting is irrelevant to pure parallel transfer.Conclusion: The statement is incorrect; parallel transfer is typically achieved with a single load/enable event, not shift pulses.
Verification / Alternative check:
Examine timing for PIPO registers: data is applied to D inputs; a single LOAD edge captures the entire word.
Why Other Options Are Wrong:
Correct: Would imply parallel transfer needs serial-like shifting, which is false.Only true for serial-in/parallel-out: That case is serial loading; the prompt is about parallel between registers.Depends on the number of bits: Bit width does not change the parallel capture mechanism.
Common Pitfalls:
Confusing bus-wide parallel moves with shift-register operations.Overlooking required control strobes (LOAD/WRITE) for proper capture.
Final Answer:
Incorrect
Discussion & Comments