Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:
Manufacturers specify timing with two complementary propagation delays: tPLH (low-to-high) and tPHL (high-to-low). For clocked devices such as flip-flops, these delays are measured from the active clock edge to the resulting transition at Q. Understanding these labels is crucial for timing closure and clock-speed calculations.
Given Data / Assumptions:
Concept / Approach:
tPLH is the time interval between the reference instant (typically the 50% point of the triggering clock edge) and the 50% point of the output's rising transition. Similarly, tPHL is measured for a falling output transition. These metrics quantify the internal response time and help compute data-path delays and setup/hold slacks in synchronous systems.
Step-by-Step Solution:
Identify the triggering clock edge (rising or falling by device specification).Mark the reference (50%) crossing of that edge as t=0.Observe the output transition; if it is LOW→HIGH, measure to its 50% point.The measured interval is tPLH, by definition.
Verification / Alternative check:
Consult any standard logic family datasheet: the timing diagrams label tPLH/tPHL exactly as described, for both combinational and sequential devices.
Why Other Options Are Wrong:
“Incorrect” misstates the conventional definition. “Only for asynchronous inputs” is wrong; the measurement reference is the clock edge, not asynchronous input changes. “Only for combinational gates” is false; the same naming convention applies to clocked devices with the clock edge as reference.
Common Pitfalls:
Confusing which transition (output or input) the L/H refers to; measuring from wrong reference points; ignoring clock-to-Q differences among families.
Final Answer:
Correct
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