Flip-flop asynchronous controls — are PRESET and CLEAR normally synchronous? Judge the statement: “PRESET and CLEAR inputs are normally synchronous.”

Introduction / Context:
Many flip-flops provide PRESET (set) and CLEAR (reset) inputs in addition to clocked data inputs. These controls are widely used for initialization and emergency forcing of states. Understanding whether they are synchronous (honored only on clock edges) or asynchronous (immediate) is critical for reset strategies.

Given Data / Assumptions:

• Standard TTL/CMOS D and J–K flip-flops include asynchronous active-low PRESET and CLEAR pins (often labeled PRE, CLR, or direct set/reset).
• Datasheets typically denote them with independent timing specs and overriding priority.
• Some specialized synchronous reset/set devices exist but are explicitly labeled and behave differently.

Concept / Approach:
“Normally” in industry practice, PRESET and CLEAR are asynchronous: when asserted, they immediately force Q to 1 or 0 regardless of the clock, provided input pulse width meets minimum requirements. Synchronous reset/set signals are applied through the data path or synchronous control inputs and only take effect at the active clock edge.

Step-by-Step Solution:
Examine pin functions: PRE and CLR act without waiting for a clock edge.Asynchronous action overrides D/J/K data inputs.Releasing PRE/CLR returns the device to normal edge-triggered operation.Therefore the statement that they are “normally synchronous” is incorrect.

Verification / Alternative check:
Datasheet timing diagrams show direct set/reset paths with independent tPHL/tPLH, confirming asynchronous behavior.

Why Other Options Are Wrong:
“Correct” reverses standard behavior. Technology qualifiers (“only in CMOS”) or RC edge-conditioning do not change the fundamental async nature in common parts.

Common Pitfalls:
Failing to synchronize asynchronous deassertion can cause metastability; not meeting minimum pulse widths; forgetting active-low polarity.

Final Answer:
Incorrect