Introduction / Context:
Edge-triggered flip-flops are the backbone of synchronous digital systems. They capture input data at discrete instants defined by clock edges, enabling deterministic timing. Misunderstanding when data is sampled can lead to timing violations, metastability, and logic errors.
Given Data / Assumptions:
- The flip-flop is negative edge-triggered, meaning it triggers on the high-to-low transition of the clock.
- Inputs must satisfy setup and hold time requirements around that transition.
- Between edges, the internal state does not change due to data variations (ignoring asynchronous controls).
Concept / Approach:
An edge-triggered device samples around an instant—the active clock edge—not throughout the entire LOW or HIGH level. The statement that it accepts inputs only while the clock is LOW confuses level sensitivity with edge sensitivity. The correct view: the device looks at the inputs at the moment of the falling edge (with setup/hold windows), not continuously during the LOW phase.
Step-by-Step Solution:
Define negative edge-triggered: sensitive at clock falling edge.Identify sampling window: setup time before edge and hold time after edge.Compare claim: “only when clock is LOW.”Conclude: incorrect; the LOW level interval is not the sampling window for edge-triggered devices.
Verification / Alternative check:
Review timing diagrams: Q updates at the instant of the falling edge; no level-following during the constant LOW interval.
Why Other Options Are Wrong:
Correct: Would imply level-driven behavior, which is false.Depends on setup/hold only: Setup/hold define margins, not level-wide acceptance.True for master–slave only: Master–slave also acts edge-equivalent; still not “LOW-only.”
Common Pitfalls:
Confusing latches (level-sensitive) with flip-flops (edge-triggered).Ignoring setup/hold, leading to intermittent failures.
Final Answer:
Incorrect
Discussion & Comments