In sequential logic design, a level-sensitive D-type latch is said to be "transparent" when its ENABLE (or G) control is asserted. Evaluate the statement: "A D-type latch changes state and follows the D input regardless of the ENABLE level." Is this statement accurate for standard positive-level or negative-level D latches?

Introduction / Context: D-type latches are fundamental storage elements used to hold a single bit in many digital systems. They are often used to create temporary storage, to build flip-flops, and to manage timing within pipelines and interface circuits. Understanding when a D latch responds to its input (D) and when it ignores changes is critical for avoiding unintended transparency and race conditions.

Given Data / Assumptions:

• We are discussing a standard level-sensitive D latch (sometimes labeled D latch, Gated D latch, or D latch with ENABLE).
• The control input is ENABLE (also shown as G or EN). A positive-level latch is transparent when ENABLE = 1; a negative-level latch is transparent when ENABLE = 0.
• No edge-triggering is implied; this is not a D flip-flop.

Concept / Approach: A level-sensitive D latch passes the D input to Q only while ENABLE is in its active level. When ENABLE is inactive, the latch holds (stores) the last value. Thus, the latch does not “follow D regardless of ENABLE.” Instead, the ENABLE strictly gates transparency.

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