Question 1

DAC linearity metrics — “Linearity is measured by the deviation of the measured step size from the ideal step size.” Assess this definition.

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Introduction / Context: Two standard accuracy metrics for DACs (and ADCs) are differential nonlinearity (DNL) and integral nonlinearity (INL). Confusing these definitions is common. This question checks whether “linearity” is defined by step-size error, or whether that definition belongs to a different metric.Given Data / Assumptions:Ideal transfer has uniform steps of 1 LSB.Real devices show deviations in both step sizes and absolute code levels.We use conventional metrology definitions.Concept / Approach: DNL quantifies the deviation of each step size from 1 LSB. INL quantifies the deviation of the converter\u2019s actual transfer function from a straight reference line (often best-fit or end-point). Therefore, saying “linearity is measured by deviation of step size” is inaccurate; that specific deviation defines DNL, not overall linearity (INL).Step-by-Step Solution:Define DNL: DNL[k] = (actual step[k] − ideal 1 LSB) / 1 LSB.Define INL: INL[k] = (actual code edge[k] − ideal straight-line edge[k]) / 1 LSB.Conclude: The statement confuses DNL (step error) with linearity (INL).Verification / Alternative check:Check converter datasheets: specifications list both INL and DNL separately with distinct definitions and test methods.Why Other Options Are Wrong:Correct: Would mislabel DNL as “linearity.”True only for PWM DACs: The DNL/INL definitions are universal, not PWM-specific.Depends only on reference voltage: Reference affects gain/offset but not the definitional distinction between INL and DNL.Common Pitfalls:Using DNL and INL interchangeably in specifications.Ignoring whether INL is end-point or best-fit when comparing devices.Final Answer:Incorrect

Question 2

Digital storage oscilloscopes — When acquisition memory is full, does the next data point always get lost? Evaluate this statement.

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Introduction / Context: Digital storage oscilloscopes (DSOs) sample incoming signals into a finite acquisition memory. What happens when that memory is full depends on the acquisition mode, trigger mode, and instrument settings. The absolute claim that the next point is always lost oversimplifies DSO behavior and is generally false.Given Data / Assumptions:Finite memory depth determines maximum record length at a given sample rate.Common modes: single (stop on trigger), run/stop, segmented memory, roll/streaming, circular buffer.Triggers and acquisition control affect capture/overwrite policies.Concept / Approach: Many DSOs use circular buffering: the instrument continuously writes samples and, upon filling the buffer, wraps around to overwrite the oldest data. In single-shot “stop on full/stop on trigger” modes, the instrument halts acquisition at memory full rather than discarding a specific “next point.” Segmented memory can capture multiple triggered segments efficiently without losing points between segments. Therefore, saying the next data point is necessarily lost is inaccurate; behavior is mode-dependent.Step-by-Step Solution:Consider circular (rolling) mode: after filling, the write pointer wraps; no “lost next point,” just continuous overwrite of oldest samples.Consider single acquisition: the scope stops once the record is complete; no new point is taken at all.Consider segmented memory: multiple short records are stored sequentially; inter-segment gaps are controlled, not arbitrary losses.Verification / Alternative check:Check specific DSO manuals: acquisition modes explicitly define wrap/stop/segment behavior when memory limits are reached.Why Other Options Are Wrong:Correct: Overgeneralizes; many modes avoid “losing the next point” by design.True only in stop-on-full mode: Even here the scope stops; it does not “lose” a specific point.Depends only on probe attenuation: Probe attenuation affects scaling/bandwidth, not memory policy.Common Pitfalls:Assuming one vendor’s default mode represents all scopes.Ignoring segmented acquisition which optimizes memory for bursty signals.Final Answer:Incorrect

Question 3

R–2R ladder DAC (MSB rung current): In a 4-bit R–2R ladder digital-to-analog converter with reference voltage Vref = 5 V and ladder resistance R = 8 kΩ (standard notation; original “8 Ω” repaired per Recovery-First), the current flowing through the …

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Introduction / Context:An R–2R ladder DAC implements binary-weighted conversion using only two resistor values, R and 2R. Each bit drives a “rung” via a switch that connects either to the reference source or to ground, creating precise fractional currents that sum at the output node. A common point of confusion is the current associated with the most significant bit (MSB) rung and how it depends on Vref and R. This question checks your understanding of the ladder’s local branch current versus the overall output current and code-dependent current division.Given Data / Assumptions:Ideal 4-bit R–2R ladder.Vref = 5 V.R = 8 kΩ (corrected from 8 Ω to a realistic value per Recovery-First Policy).MSB switch tied to Vref when evaluating the “MSB rung current.”No output load (or a high-impedance buffer), ideal switches/resistors.Concept / Approach:In an ideal R–2R ladder, each rung contains a resistor R that, when its switch is connected to Vref, sources a current approximately equal to Vref / R into the adjacent 2R network node. While the final DAC output voltage is code-dependent due to current steering and division across the ladder, the immediate branch current through the MSB’s series R (with its switch at Vref) is set by Ohm’s law with R as the dominant element for that local path in the canonical analysis and equals 5 V / 8 kΩ = 0.625 mA = 625 µA.Step-by-Step Solution:Identify the MSB rung: series resistor R from Vref to the ladder node when the MSB switch selects Vref.Apply Ohm’s law locally: I_MSB_rung = Vref / R = 5 / 8000 A.Compute: 5 / 8000 = 0.000625 A = 0.625 mA = 625 µA.Conclude that the stated value (625 µA) matches the standard ideal-ladder result.Verification / Alternative check:Textbook derivations show that each bit’s current contribution is steered through the ladder and attenuated before reaching Vout. However, the question asks about the current through the MSB R element itself, not the net contribution at Vout. Simulation of a 4-bit ladder with 8 kΩ/16 kΩ elements confirms the branch current equals Vref / R when the MSB switch is at Vref in the ideal model.Why Other Options Are Wrong:Incorrect: Conflicts with Ohm’s law for the local series R.Ambiguous without switch position: The stem specifies the MSB tied to Vref.Depends on load only: Branch current here is dominated by R and Vref; a high-Z load is assumed.Common Pitfalls:Mixing up branch current with the proportion of that current that reaches Vout; using an unrealistic R value (8 Ω) that implies 0.625 A; forgetting the high-impedance output buffer assumption.Final Answer:Correct

Question 4

Sample-and-hold usage in converters: “A sample-and-hold (S/H) circuit is used in D/A conversion.” Decide whether this characterization is accurate and explain how S/H fits primarily in A/D conversion and how DAC outputs are typically held.

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Introduction / Context:Sample-and-hold (S/H) circuits momentarily capture analog values so that conversion or processing can occur on a stable signal. Understanding where S/H is essential—A/D or D/A—prevents architectural mistakes and clarifies why many converter datasheets include or omit S/H blocks.Given Data / Assumptions:S/H circuit definition: track an analog input, then hold a snapshot for a defined interval.Comparing roles in ADCs versus DACs.Assume conventional architectures (SAR, pipeline, delta-sigma for ADCs; current-steering, R–2R, or string for DACs).Concept / Approach:In A/D conversion, holding the input prevents it from changing during the successive decision process (e.g., SAR bit trials) or during pipeline stages, ensuring accuracy. Thus, S/H is a core element in many ADCs. In D/A conversion, the converter produces a new analog level from a digital code. To keep the analog output steady between code updates, DACs inherently act as a zero-order hold (ZOH), often followed by an output buffer or a reconstruction filter—not a classical front-end “sample-and-hold” on an analog input. Therefore, the blanket statement that S/H is used in D/A conversion is misleading.Step-by-Step Solution:Identify ADC need: stabilize a changing analog input → S/H before quantization.Identify DAC behavior: output steps held by output latches/buffers (ZOH) until next update.Conclude: S/H is primarily associated with ADCs; DACs rely on output latching/filters.Hence, the statement as written is inaccurate.Verification / Alternative check:Review SAR ADC block diagrams (track/hold + comparator + DAC). Review DAC diagrams (latches + switching core + output buffer + RC filter). The roles differ fundamentally.Why Other Options Are Wrong:Correct: Would conflate S/H with DAC output holding functions.Ambiguous; depends on architecture: While nuances exist, the general statement is still inaccurate.Applies only to SAR ADCs: Pipelines and other ADCs also use S/H.Common Pitfalls:Calling the DAC output latch a “sample-and-hold”; ignoring reconstruction filtering requirements for DAC outputs.Final Answer:Incorrect

Question 5

Up-counter driving a 4-bit DAC: “When the inputs of a 4-bit D/A converter are driven by a binary up-counter, the analog output looks like an upward sloping line.” Evaluate this description.

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Introduction / Context:A binary up-counter feeding a DAC is the basis of a staircase generator. Many texts informally say it “ramps up,” but the precise shape at the DAC output is key for understanding quantization effects and reconstruction filtering.Given Data / Assumptions:4-bit DAC, ideal behavior.Binary up-counter increments by 1 code per tick.No post-DAC low-pass smoothing unless stated.Concept / Approach:The DAC maps each successive code to a discrete analog level separated by one LSB. As the counter increments, the output steps upward by fixed increments, forming a staircase, not a continuous sloped line. A continuous ramp can be approximated only after low-pass filtering (reconstruction), which smooths the steps by integrating high-frequency components from the sampling process.Step-by-Step Solution:Counter counts: 0000, 0001, 0010, …, 1111.DAC outputs corresponding levels Vout = k * LSB for k = 0..15.Plotting Vout versus time shows flat segments with sudden rises → staircase.Continuous ramp arises only after intentional filtering; not inherent to the raw DAC output.Verification / Alternative check:Oscilloscope traces of DAC outputs driven by counters show step-and-hold behavior. Applying an RC or active low-pass can make the envelope look like a ramp, but the raw output remains quantized steps.Why Other Options Are Wrong:Correct: Ignores quantized nature of DAC output.Only true after heavy filtering: That caveat is accurate, but the stem did not include it; as written, the claim is false.Ambiguous: Update rate does not change the stepped nature without filtering.Common Pitfalls:Equating “monotonic increasing” with “line”; forgetting LSB granularity; assuming infinite update rate eliminates steps (it does not).Final Answer:Incorrect

Question 6

Data acquisition buses: A data acquisition (DAQ) subsystem may communicate over two common buses: a data bus and a control bus (with addressing provided separately or embedded). Assess the statement.

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Introduction / Context:DAQ systems interface sensors and actuators to processors. Communication structures vary (parallel buses, SPI/I2C, PCIe). Conceptually, interactions can be viewed as data transfer plus control/handshaking, which many curricula summarize as “data bus” and “control bus.” Addressing may be explicit (address bus) or encoded within control transactions, especially in serial protocols.Given Data / Assumptions:General DAQ subsystem attached to a host processor or controller.Parallel or serial interconnects are possible.Address information may be carried on a dedicated bus or multiplexed.Concept / Approach:The classical parallel microprocessor model uses three groups: address, data, and control. Many practical DAQ links collapse address into commands or registers accessed over the control path. Thus, describing communication in terms of a data bus (payload) and a control bus (commands, strobes, status) is acceptable in a generic sense, even though specific implementations may expose a separate address bus.Step-by-Step Solution:Identify payload path: data bus transfers samples, configuration values, and results.Identify orchestration: control bus conveys read/write strobes, chip selects, start/ready flags, interrupts.Addressing may be distinct (parallel bus) or embedded (serial command frames).Therefore the two-bus description is functionally valid for many DAQ contexts.Verification / Alternative check:Datasheets for ADC/DAC/DAQ cards show separate data width and control signaling; serial devices define command opcodes (control) distinct from payload bits (data).Why Other Options Are Wrong:Incorrect: Overly rigid; many DAQ implementations follow the two-bus functional view.Only true with serial DAQs: Not limited to serial; applies to parallel too.“Always three buses”: Some designs multiplex address; “always” is false.Common Pitfalls:Assuming a strict three-bus taxonomy in all systems; ignoring protocol-layer multiplexing of address within control frames.Final Answer:Correct

Question 7

ADC output nature: “The output of an analog-to-digital converter (ADC) is a voltage level.” Decide whether this is accurate and clarify what an ADC actually produces.

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Introduction / Context:ADCs bridge the analog and digital domains. Misunderstanding the nature of their outputs leads to wiring mistakes and unrealistic expectations about driving loads or analog circuits directly from an ADC port.Given Data / Assumptions:Generic ADC device, any architecture (SAR, pipeline, delta-sigma, flash).Digital interface present (parallel bus or serial SPI/I2C/LVDS).Reference voltage defines scale but not output type.Concept / Approach:An ADC samples an analog input and outputs a digital code—a binary word representing the quantized value relative to its reference. This code is conveyed as logic-level signals (0/1) across its digital interface. The only analog pins on an ADC normally are the analog input(s), reference, and sometimes clock or bias pins; the data pins are digital, not analog voltage outputs representing the measurement magnitude in proportional amplitude.Step-by-Step Solution:ADC samples Vin and compares it to quantization thresholds.Produces an N-bit code (e.g., 12-bit word) representing Vin.Transfers the code via digital lines or serial frames.Downstream logic interprets the code; any analog reconstruction requires a DAC, not the ADC.Verification / Alternative check:Consult any ADC timing diagram: outputs are labeled D[N-1:0] with logic-level specs (VOH, VOL), setup/hold, and clock requirements. No “analog voltage output proportional to Vin” is specified.Why Other Options Are Wrong:Correct: Confuses ADCs with DACs.Only true for flash converters: Flash refers to comparator array architecture, still producing digital codes.Ambiguous: Reference voltage affects scale, not output modality.Common Pitfalls:Expecting to feed an analog meter from an ADC pin; ignoring the need for a DAC or PWM/filter to generate analog voltages from digital codes.Final Answer:Incorrect

Question 8

Tracking (servo) ADC behavior at a steady input: “When the analog input to a tracking A/D converter is constant, the digital output will oscillate around the true code.” Evaluate this behavior.

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Introduction / Context:Tracking (a.k.a. servo or up/down) ADCs adjust their output code one LSB at a time to follow the input. Understanding their steady-state behavior clarifies why they are simple but relatively slow to acquire large step changes and why they show code toggling even for constant inputs near decision thresholds.Given Data / Assumptions:Tracking ADC that increments/decrements a DAC until Vdac matches Vin within 1 LSB.Constant, noise-free Vin (practically, small noise exists).Ideal quantizer with finite resolution.Concept / Approach:In a tracking ADC, a comparator evaluates (Vin − Vdac). If positive, the logic increments the code; if negative, it decrements. With a constant Vin not exactly at a quantization center, the loop hunts between the nearest two adjacent codes. Even with a centered value, thermal/comparator noise usually produces occasional toggling (limit-cycle behavior). Hence, the digital output “oscillates” by ±1 LSB around the best representation.Step-by-Step Solution:Initialize code near the expected value.Comparator drives increment/decrement decisions each cycle.For steady Vin, the loop converges to the two bounding codes.Resulting output shows alternating codes (dither) within ±1 LSB.Verification / Alternative check:Loop analysis reveals a limit cycle when the error cannot be reduced below 0.5 LSB. Simulations or bench tests show a square-wave-like flipping between two codes for DC inputs near thresholds.Why Other Options Are Wrong:Incorrect: Would imply perfect static holding, which contradicts the algorithm.Only true with noisy references: Noise amplifies the effect but is not required for the basic limit cycle.Ambiguous: Resolution does not eliminate ±1 LSB hunting; it sets the step size.Common Pitfalls:Expecting rock-solid constant codes from tracking ADCs; overlooking the need for output averaging or hysteresis to stabilize readouts.Final Answer:Correct

Question 9

DAC monotonicity criterion: “A DAC is monotonic if its output strictly increases whenever its binary input code is incremented to the next higher value.” Assess this definition.

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Introduction / Context:Monotonicity is a critical DAC property for closed-loop control and instrumentation. A nonmonotonic DAC can reverse direction for some code step, causing control loops to become unstable or measurements to glitch. Understanding the formal definition distinguishes it from linearity metrics such as DNL and INL.Given Data / Assumptions:Binary-weighted codes; assume ideal coding (e.g., straight binary).Increment by 1 LSB in digital code.Evaluate output change with each step.Concept / Approach:Monotonic means “never decreases when the input code increases.” A strictly increasing (or at least nondecreasing) analog output over the entire code range satisfies monotonicity. DNL (differential nonlinearity) less than 1 LSB guarantees monotonicity; if DNL exceeds 1 LSB, negative steps can occur, breaking monotonic behavior. The concise statement in the question aligns with the practical definition used in datasheets and control literature.Step-by-Step Solution:Consider code k and k+1.Compute ideal step: V(k+1) − V(k) = 1 LSB (positive).Real DAC: step size may vary due to DNL, but must not be negative.Hence, “output increases as input increments” captures monotonicity.Verification / Alternative check:Datasheets explicitly state “monotonic to N bits” and relate it to maximum DNL. Testing involves scanning codes and ensuring no downward transitions occur.Why Other Options Are Wrong:Incorrect: Opposes standard terminology.Only true for current-steering: Architecture-independent property.Ambiguous; needs INL: INL does not define monotonicity; DNL does.Common Pitfalls:Confusing monotonicity with absolute accuracy; believing an INL of 0 is required (it is not).Final Answer:Correct

Question 10

Converter usefulness criterion: “For A/D and D/A converters to be useful, there must be a meaningful mapping between the analog quantity and its digital representation, and vice versa.” Determine whether this statement is valid.

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Introduction / Context:Converters bridge the analog and digital realms. Their utility rests on a predictable, calibrated relationship between physical quantities (voltage, current, temperature via sensors) and digital codes (binary words). Without a defined mapping, measurements and actuations would be uninterpretable.Given Data / Assumptions:ADC: maps analog input to digital code using a transfer function.DAC: maps digital code to analog output using a reconstruction function.“Meaningful” implies monotonicity, documented scaling, and tolerances.Concept / Approach:A converter’s transfer function defines the code-to-quantity relationship. Linearity (or a known nonlinearity), gain/offset, monotonicity, resolution, and noise determine how well codes represent real-world values. Calibration or specifications ensure that a given code corresponds to a predictable analog value within error bounds. The reverse mapping must be equally defined so a desired analog level can be commanded digitally. Therefore, the statement captures the essence of converter utility.Step-by-Step Solution:Define ADC transfer: Code = f(Vin, Vref) with documented LSB = FS/2^N.Define DAC transfer: Vout = g(Code, Vref) with known step size and errors.Ensure monotonicity and bounded INL/DNL for predictability.Result: bidirectional, interpretable mapping exists.Verification / Alternative check:Calibration procedures and datasheet specs (gain, offset, INL/DNL, noise) provide the mapping accuracy that systems rely on for sensing and control.Why Other Options Are Wrong:Incorrect: Would deny the fundamental purpose of converters.Only true for linear converters: Nonlinear mappings are also “meaningful” if defined.Ambiguous: Coding (offset binary, two’s complement) still yields a documented mapping.Common Pitfalls:Confusing resolution with accuracy; ignoring reference stability and calibration in defining the mapping.Final Answer:Correct

Question 11

DAC error terminology: “When a DAC’s measured step sizes deviate from the ideal 1 LSB step size, the error is called nonlinearity.” Judge this statement.

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Introduction / Context:Precision DACs are characterized by several error metrics. Distinguishing offset, gain, differential nonlinearity (DNL), and integral nonlinearity (INL) is fundamental for specifying accuracy and control-loop stability. The question targets the concept of nonlinearity as it relates to step size deviations.Given Data / Assumptions:Ideal step size = 1 LSB in a nominally linear DAC.Measured step sizes may vary due to mismatch and circuit nonidealities.We focus on deviations from ideal steps and their classification.Concept / Approach:DNL quantifies how much each individual code-to-code step differs from 1 LSB. INL quantifies cumulative deviation of the transfer curve from a straight line (best-fit or endpoint). Thus, “deviation of the measured step size from the ideal step size” directly describes DNL, which is a form of nonlinearity. Therefore, the statement is correct in the general sense that such deviations fall under nonlinearity errors.Step-by-Step Solution:Define ideal transfer: equally spaced steps of 1 LSB.Measure actual steps; compute DNL = (actual step − 1 LSB) / 1 LSB.Aggregate deviations across codes to assess monotonicity risk (DNL Recognize INL as the overall curve deviation metric.Verification / Alternative check:Datasheets list DNL and INL separately under “nonlinearity.” Step size variation appears explicitly in DNL plots.Why Other Options Are Wrong:Incorrect: Conflicts with standard definitions.Offset error: A uniform shift of the whole curve, not step deviation.Ambiguous due to reference: Reference drift shifts the scale but does not define nonlinearity by itself.Common Pitfalls:Confusing gain error (slope) and offset error with nonlinearity; assuming INL alone captures all step deviations.Final Answer:Correct

Question 12

Eight-bit DAC resolution claim: “An 8-bit D/A converter has a resolution of 0.125.” Evaluate the accuracy; state the correct resolution as a fraction and percentage of full scale.

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Introduction / Context:Resolution defines the smallest analog change a DAC can produce for a one-code increment, expressed as a fraction of full scale (FS) or as a percentage. Correctly calculating resolution is foundational in sizing converters for measurement and control applications.Given Data / Assumptions:N = 8 bits.Ideal DAC with 2^N discrete levels.Resolution refers to 1 LSB relative to FS.Concept / Approach:For an N-bit DAC, the number of codes is 2^N. The LSB size, as a fraction of full scale, is 1 / (2^N). Thus, for N = 8, resolution = 1 / 256 ≈ 0.00390625 FS, which equals 0.390625%. The claim “0.125” (unitless) does not match any standard expression for 8-bit resolution; 0.125 corresponds to 1/8 or 12.5%, which would be the resolution of a 3-bit DAC (1/2^3).Step-by-Step Solution:Compute 2^8 = 256.Resolution = 1 / 256 ≈ 0.00390625 of FS.As a percentage: 0.00390625 * 100 = 0.390625% of FS.Compare to 0.125 (12.5%): mismatched by a factor of 32.Verification / Alternative check:General formula holds for all N: Resolution% = 100 / (2^N). For N = 3, this gives 12.5% (0.125), confirming that 0.125 aligns with 3-bit, not 8-bit resolution.Why Other Options Are Wrong:Correct: Would imply 8-bit steps of 12.5% FS—clearly incorrect.Only true for 3-bit DACs: This is a helpful comparison but the stem claims 8-bit.Ambiguous: Even without units, 0.125 as a fraction or decimal is not 1/256.Common Pitfalls:Confusing number of levels (2^N) with number of steps (2^N − 1); forgetting to specify units (fraction vs percent) leading to misinterpretation.Final Answer:Incorrect

Question 13

Binary-weighted DAC (4-bit) resistor sizing: If the least significant bit (LSB) of a four-bit binary-weighted resistor D/A converter uses a 200 Ω resistor, determine whether the resistor for the next more significant bit should be 100 Ω.

Accepted Answer

Introduction / Context:Binary-weighted D/A converters generate an analog output by summing currents (or voltages) that are proportional to binary bit weights. Each more significant bit must contribute exactly twice the effect of the next less significant bit. The easiest way to achieve this with a resistor-weighted DAC is to halve the resistance for each step toward the most significant bit (MSB), thereby doubling the current for a given reference voltage. This item checks your understanding of that geometric scaling rule.Given Data / Assumptions:Architecture: binary-weighted resistor DAC (not an R-2R ladder).Four-bit resolution: bits are LSB, next bit, next bit, MSB.LSB resistor value is 200 Ω, driven by the same Vref as other bits.Ideal switches and op-amp summing node assumed for clarity.Concept / Approach:For a resistor-weighted DAC that sums currents into a virtual ground, bit current is I_bit = Vref / R_bit when the switch is ON. To double the contribution when moving one position toward the MSB, we must double the current. With a constant Vref, doubling current requires halving the resistance. Hence, if the LSB uses 200 Ω, the next bit should use 100 Ω, then 50 Ω, and so on, reaching the smallest value at the MSB.Step-by-Step Solution:Identify weighting rule: each step toward MSB must produce 2 * current.Hold Vref constant; therefore I ∝ 1/R.Given R_LSB = 200 Ω → next bit needs 200 Ω / 2 = 100 Ω.Verification / Alternative check:If the four resistors are 200 Ω (LSB), 100 Ω, 50 Ω, and 25 Ω (MSB), their ON currents form 1:2:4:8, exactly matching binary weights. Summing these currents via an op-amp produces a linear transfer characteristic (ignoring switch/amp nonidealities).Why Other Options Are Wrong:Incorrect: Violates the binary current-doubling rule.Only if Vref is halved: Vref is common to all bits; scaling is via R.Only for R-2R ladders: R-2R uses equal-value parts; statement concerns binary-weighted type.Depends on op-amp slew: Slew affects speed, not ideal static scaling.Common Pitfalls:Confusing the binary-weighted scheme with the R-2R ladder (which does not use powers-of-two resistors) and assuming Vref changes per bit. In a proper design, Vref is fixed and resistor values enforce weighting.Final Answer:Correct

Question 14

Quantization levels vs. resolution: With 4-bit resolution, is it possible to obtain more than 16 distinct analog output levels from an ideal DAC?

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Introduction / Context:Resolution defines how many discrete codes a converter can represent. An ideal n-bit DAC has 2^n unique digital codes and therefore 2^n analog output steps. This question probes whether learners equate “4-bit resolution” with a precise, finite set of quantization levels and resist the temptation to assume extra levels can be created without changing resolution.Given Data / Assumptions:Ideal, memoryless 4-bit DAC (no dynamic tricks).Uniform code mapping across its defined output span.No dithering, averaging, or time-domain modulation considered in the static sense.Concept / Approach:For an ideal DAC, the number of distinct output levels equals the number of input codes: 2^n. With n = 4, that is 16 levels. Each step is one least significant bit (LSB) in amplitude. Although advanced techniques such as oversampling with noise shaping, pulse-width modulation, or time-averaging can effectively increase apparent resolution over time, the instantaneous static output still presents one of the 16 levels at any sample instant for a pure 4-bit DAC core.Step-by-Step Solution:Compute levels: 2^n → 2^4 = 16.Interpret properly: “More than 16” contradicts the definition of 4-bit resolution.Conclude: The statement is not valid for an ideal static DAC.Verification / Alternative check:Look at a 4-bit transfer characteristic: a staircase with 16 steps from code 0000 to 1111. No intermediate static plateaus exist without extra modulation or analog filtering of a higher-rate bitstream.Why Other Options Are Wrong:Correct / oversampling / noise shaping: These refer to techniques that improve effective resolution over time, not the core static number of levels.Depends on Vref: Vref sets absolute amplitudes, not the count of distinct levels.Common Pitfalls:Confusing effective number of bits (ENOB) improvements from dynamic methods with the inherent code count of the DAC.Final Answer:Incorrect

Question 15

Settling time comparison: In general, do current-output DACs settle faster than voltage-output DACs of similar resolution and technology?

Accepted Answer

Introduction / Context:Settling time is the interval a DAC output needs to reach and remain within a specified error band after a code transition. Architecture significantly affects it. Current-steering DACs (current-output) often switch matched current sources directly and hand the summing to a transimpedance node, while voltage-output DACs integrate an internal amplifier that must slew and settle, adding dynamics that can slow the response.Given Data / Assumptions:Comparable process and resolution (e.g., 8–16 bits).Proper output compliance for current DACs; suitable I/V op-amp bandwidth.No excessive output loading or layout parasitics skewing results.Concept / Approach:Current-output (current-steering) DACs use fast switching of current cells; the external I/V converter can be optimized for bandwidth. Voltage-output DACs include an internal amplifier that must slew across step changes and recover from glitches, typically producing longer worst-case settling times. Consequently, for high-speed applications (communications, waveform synthesis), current-output DACs are preferred when fast settling and wide bandwidth are priorities.Step-by-Step Solution:Consider architecture: switching currents vs. slewing an internal op-amp.Assess dynamics: current steering minimizes internal settling bottlenecks.Conclude: current-output DACs generally settle faster.Verification / Alternative check:Datasheets commonly show sub-100 ns settling for current-output devices of a given resolution, whereas comparable voltage-output devices list longer settling times due to amplifier dynamics and output buffer stabilization.Why Other Options Are Wrong:“Incorrect”: Contradicts widely observed architectural behavior.“Only true for 16-bit” / “below 1 kHz”: Not tied to a single resolution or rate; it is architectural.“Depends solely on reference”: Reference design matters but is not the sole determinant.Common Pitfalls:Ignoring the external I/V op-amp requirements for current-output DACs; a poor I/V stage can negate the advantage.Final Answer:Correct

Question 16

Direction of conversion (definitions check): D/A conversion takes a voltage or current and converts it to a digital code. Evaluate this statement.

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Introduction / Context:Clear terminology prevents design confusion. D/A and A/D mark opposite directions of signal conversion at the digital–analog boundary. This question checks whether you can correctly associate the direction with the acronym and not mix them up during specification or troubleshooting.Given Data / Assumptions:D/A (DAC) and A/D (ADC) devices are idealized for definition purposes.Input/output ranges are within specified compliance and reference limits.We focus on the direction of conversion, not the particular architecture.Concept / Approach:A Digital-to-Analog Converter (DAC) accepts a digital code at its input and produces a corresponding analog quantity (voltage or current) at its output. Conversely, an Analog-to-Digital Converter (ADC) accepts an analog quantity and outputs the corresponding digital code. Therefore, the statement “D/A conversion takes a voltage or current and converts it to a digital code” actually describes the ADC, not the DAC, and is thus incorrect.Step-by-Step Solution:Identify D/A: digital in → analog out.Identify A/D: analog in → digital out.Compare with the statement: it describes A/D; therefore the claim about D/A is wrong.Verification / Alternative check:Block diagrams in textbooks and datasheets consistently show “DAC: code → voltage/current” and “ADC: voltage/current → code.” This is independent of topology (flash, SAR, sigma-delta, current-steering, R-2R ladder).Why Other Options Are Wrong:“Correct” and architecture-specific options conflate direction with topology; direction is universal.Bipolar/unipolar range affects scaling and offset, not conversion direction.Common Pitfalls:Mixing up terms when discussing mixed-signal interfaces; always state which device (ADC or DAC) and the direction explicitly.Final Answer:Incorrect

Question 17

Static linearity metrics: “Linearity error is the maximum deviation in step size from the ideal step size.” Evaluate this definition.

Accepted Answer

Introduction / Context:Two commonly reported static accuracy metrics for data converters are Differential Nonlinearity (DNL) and Integral Nonlinearity (INL). Although both concern linearity, they quantify different aspects. Confusing them leads to misinterpretation of datasheets and incorrect performance predictions.Given Data / Assumptions:DNL and INL are defined relative to an ideal DAC transfer curve.“Step size” refers to the output change when incrementing the code by one LSB.Ideal DAC step size is constant over the entire transfer characteristic.Concept / Approach:DNL is the maximum deviation of any actual code-to-code step size from one ideal LSB. In words: “maximum deviation in step size from ideal step size” fits DNL. By contrast, INL (often called linearity error) is the maximum deviation of the DAC’s actual transfer function from a straight reference line (endpoint or best-fit line). INL reflects accumulated error across codes, not individual step distortions.Step-by-Step Solution:Map statement to metric: “deviation in step size” → DNL.Define INL: “max deviation of the overall transfer from a line.”Therefore, the statement is not a correct definition of linearity error (INL).Verification / Alternative check:Consult converter literature: plots of DNL show step-by-step differences; INL plots show cumulative deviation versus an ideal straight line. A device may have low DNL yet show noticeable INL, and vice versa.Why Other Options Are Wrong:Claiming “Correct (INL)” inverts definitions.Monotonic/FSR/calibration caveats do not change the definitions; they affect behavior or correction, not nomenclature.Common Pitfalls:Assuming monotonicity from good INL alone; monotonicity relates more directly to DNL staying above −1 LSB.Final Answer:Incorrect (that describes DNL, not linearity error)

Question 18

Historical 8-bit DACs: Evaluate: “The DAC0808 and the MC1408 are popular, low-cost, 8-bit D/A converters (current-output type).”

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Introduction / Context:The DAC0808 and its Motorola/ON counterpart MC1408 are classic 8-bit DACs widely used in education and industry. They are inexpensive, easy to interface, and represent the canonical example of a current-output DAC that requires an external I/V converter to produce a voltage output.Given Data / Assumptions:Resolution: 8 bits.Architecture: current-output, weighted or segmented internally.Typical use: pair with an op-amp transimpedance stage for voltage output.Concept / Approach:These devices sink/source a controlled output current proportional to the applied digital code and reference. Because they are current-output, applications commonly include an op-amp configured as a transimpedance amplifier to generate a voltage with desired polarity and scaling. Their popularity stems from availability, cost, and abundant example circuits in textbooks and application notes.Step-by-Step Solution:Identify device type: DAC0808/MC1408 are 8-bit current-output DACs.Note interface: parallel digital inputs, reference current, and Iout pins.Recognize external I/V conversion for voltage output.Verification / Alternative check:Typical specifications list full-scale current, compliance voltage, reference requirements, and settling times, confirming current-output behavior and 8-bit resolution.Why Other Options Are Wrong:“Incorrect”: Contradicts well-documented device characteristics.“Only with R-2R ladders”: They are themselves DAC ICs; external R-2R is not required.“Voltage-output parts”: False; voltage output requires an external op-amp.“Depends on temperature grade”: Temperature affects accuracy/drift, not the basic description.Common Pitfalls:Forgetting to include an I/V stage and compliance limits, leading to linearity issues.Final Answer:Correct

Question 19

Flash ADC trade-off: The main disadvantage of the flash (simultaneous) A/D converter architecture is the large number of required comparators. Evaluate this statement.

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Introduction / Context:Flash A/D converters achieve extraordinary speed by comparing the input simultaneously against many reference thresholds and encoding the result. This parallelism trades silicon area and power for speed. The question asks whether the comparator count is the principal drawback.Given Data / Assumptions:n-bit flash ADC requires 2^n − 1 comparators.Resistor ladder generates evenly spaced thresholds.High-speed thermometer-to-binary encoding is included.Concept / Approach:Because comparator count grows exponentially with resolution, area, input capacitance, power consumption, and offset calibration complexity all increase rapidly. For example, 8 bits needs 255 comparators; 10 bits would need 1023, which is usually impractical. Hence, the overwhelming disadvantage is the large comparator array, making flash ADCs suitable for low-resolution, very-high-speed roles (e.g., 6–8 bits at hundreds of MS/s to GS/s) rather than medium/high-resolution applications.Step-by-Step Solution:Relate comparator count to bits: N_cmp = 2^n − 1.Assess impact: area, power, matching, and calibration scale with N_cmp.Conclude: comparator count is the dominant limitation.Verification / Alternative check:Most medium/high-resolution ADCs adopt SAR, pipeline, or sigma-delta architectures specifically to avoid exponential comparator scaling.Why Other Options Are Wrong:“Incorrect”: Ignores the exponential scaling reality.Bit-range or input-polarity caveats miss the fundamental architectural trade-off.Aperture jitter affects sampling accuracy but is not the cause of the comparator-count disadvantage.Common Pitfalls:Assuming flash is universally best due to speed; for many applications, power and area budgets dominate.Final Answer:Correct

Question 20

Flash ADC encoding method: A simultaneous (multiple-comparator) or flash A/D converter uses parallel encoding. Evaluate this statement.

Accepted Answer

Introduction / Context:In a flash ADC, the input is compared simultaneously to many reference levels, and the set of comparator outputs forms a thermometer code. This must then be converted, or encoded, into a binary number by a parallel digital encoder. The statement tests recognition of that parallel nature.Given Data / Assumptions:Architecture: flash/simultaneous ADC.Comparator bank produces a thermometer code.Digital block performs thermometer-to-binary encoding concurrently.Concept / Approach:Because all thresholds are tested at the same instant, the encoding is inherently parallel: the complete code word is produced without iterative steps. This sharply contrasts with SAR ADCs (which perform sequential approximation) and sigma-delta ADCs (which shape and decimate a 1-bit or few-bit stream). Therefore, saying flash ADCs “use parallel encoding” is accurate.Step-by-Step Solution:Input is fanned out to 2^n − 1 comparators.Comparator outputs form a thermometer pattern.Parallel encoder maps thermometer to binary code in one operation.Verification / Alternative check:Block diagrams for flash converters always show ladder, comparator array, and a fast encoder; there is no iterative decision loop.Why Other Options Are Wrong:Bit-depth and differential-input caveats do not change the encoding principle.Half-flash still uses parallel comparator groups with encoding stages.Common Pitfalls:Confusing the parallel encoding of flash with pipeline stages or SAR bit trials; only flash produces the full code in a single comparison step.Final Answer:Correct

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