Question 1

Sensors and interfacing – definition of a transducer in instrumentation A transducer is a device that:

Accepted Answer

Introduction / Context:Instrumentation and control systems rely on transducers to translate real-world phenomena into electrical signals that electronics can process. Recognizing the correct definition is foundational for sensor selection and signal conditioning. Given Data / Assumptions: “Physical variable” may include temperature, pressure, light, motion, force, etc. Electronics typically require a voltage, current, resistance, or frequency to represent that variable. Concept / Approach:A transducer performs energy conversion from one domain to another. In measurement systems we usually mean conversion from a physical domain to an electrical domain (e.g., thermocouple, strain gauge, photodiode). Actuators are the converse (electrical to physical). Data processing/storage functions are not transduction. Step-by-Step Solution: Identify the standard measurement-system role: physical → electrical.Map examples: pressure sensor outputs voltage; light sensor outputs current.Select the definition matching this role. Verification / Alternative check:Textbooks define a transducer as a device that converts energy from one form to another; in sensor contexts the conversion is to an electrical signal proportional to the measurand. Why Other Options Are Wrong: Converts analog data to meaningful data: That is signal processing, not transduction. Controls a physical variable: That describes an actuator or controller. Stores and processes digital data: That describes a computer or digital system, not a transducer. Common Pitfalls: Confusing sensors (transducers) with actuators or with processing electronics. Final Answer:converts a physical variable to an electrical variable

Question 2

DAC verification – practical method for testing a digital-to-analog converter What is the basic, effective approach to test a D/A converter over its operating range?

Accepted Answer

Introduction / Context:Testing DACs involves verifying monotonicity, resolution, and linearity. A practical bench method examines the converter's response to all digital input codes and inspects the analog output for expected behavior. Given Data / Assumptions: D/A converter under test; output can be observed on an oscilloscope or precision DMM. Full digital input code range is available. We want a quick but thorough functional check. Concept / Approach:Feeding the DAC a count sequence from 0 to full scale and plotting output versus time should yield a monotonic staircase that approximates a straight ramp after filtering. This reveals missing codes, nonlinearity, glitches, and monotonicity violations. Spot checks at only two points (zero and full scale) do not validate intermediate behavior. Step-by-Step Solution: Drive DAC inputs with an up-counting binary counter through all codes.Observe output: a staircase rising in equal steps (LSB size).Assess linearity by comparing the staircase to a straight line; look for missing steps or reversals. Verification / Alternative check:Alternatively, capture pairs (digital code, analog output) and compute INL/DNL numerically; the oscilloscope method is a fast qualitative equivalent. Why Other Options Are Wrong: Single-step with DMM: Better than two points, but too slow and still easy to miss dynamic issues/glitches. Zero and full scale only: Does not detect missing codes or nonlinearity. Applying analog to DAC and checking digital: Reversed; that describes ADC testing. Common Pitfalls: Using insufficient settling time per code and misinterpreting transient glitches as errors. Failing to ensure reference stability and low-noise grounding during measurement. Final Answer:apply a sequence of binary codes covering the full range … linear stairstep ramp

Question 3

ADC accuracy – identifying common causes of conversion errors Which of the following can directly cause inaccurate analog-to-digital conversion results in practical systems?

Accepted Answer

Introduction / Context:Accurate ADC measurements require a stable input during conversion and proper front-end behavior. Many architectures depend on a sample-and-hold (S/H) to freeze the input so the converter sees a constant voltage while it works. Given Data / Assumptions: An ADC and its front-end are being evaluated for accuracy issues. We consider typical error sources in mixed-signal systems. Concept / Approach:A faulty or underperforming sample-and-hold causes droop, aperture uncertainty, or feedthrough during conversion, introducing conversion errors, especially with fast or noisy signals. By contrast, a stable constant input is ideal; a generic “linear ramp” is not inherently inaccurate; and intermittent counter inputs usually refer to digital control problems rather than intrinsic conversion inaccuracy unless they affect timing catastrophically (a separate fault domain). Step-by-Step Solution: Identify the block that must maintain a stable voltage: the S/H.Recognize that faults in S/H (droop, slew limits, charge injection) corrupt the held value.Conclude that faulty S/H directly causes conversion inaccuracy. Verification / Alternative check:Datasheets specify S/H acquisition time, droop rate, and aperture jitter. Violations of these specs or a failed S/H manifest as inconsistent or biased codes. Why Other Options Are Wrong: Constant analog input voltage: Beneficial for accuracy; not a cause of error. Linear ramp usage: Common in testing; not inherently inaccurate. Intermittent counter inputs: A digital control issue; may stop conversions but is not the primary analog accuracy limiter compared to S/H failure. Common Pitfalls: Blaming the ADC core while ignoring front-end hold conditions, source impedance, and reference stability. Final Answer:faulty sample-and-hold circuitry

Question 4

Successive-approximation ADC timing For an 8-bit successive-approximation (SAR) analog-to-digital converter clocked at 20 kHz, what is the maximum conversion time per sample (assume 1 comparison per bit and ignore minor overhead)?

Accepted Answer

Introduction / Context:A successive-approximation (SAR) ADC performs one binary search step per bit to decide the output code. The conversion time is tied directly to the ADC clock period and the number of bits, so being able to compute the worst-case conversion time is a core practical skill in data acquisition and embedded systems. Given Data / Assumptions: N = 8 bits. Clock frequency f_clk = 20 kHz. Ideal SAR timing: 1 clock per comparison, so conversions require approximately N clocks. Minor overheads (track/hold, start, end) are ignored as directed. Concept / Approach:For a SAR converter, conversion_time ≈ N * T_clk, where T_clk = 1 / f_clk. Each bit decision takes one clock (trial via the internal DAC and comparator), so an 8-bit decision takes 8 clocks in the worst case. Step-by-Step Solution:Compute clock period: T_clk = 1 / 20,000 = 50 µs.Multiply by number of bits: T_conv ≈ 8 * 50 µs.T_conv ≈ 400 µs.Convert to milliseconds: 400 µs = 0.4 ms. Verification / Alternative check:Rule of thumb: a SAR ADC roughly needs as many clock cycles as bits. For 8 bits at 20 kHz, 20,000 / 8 ≈ 2,500 samples per second, giving 0.4 ms per conversion, which matches the calculation above. Why Other Options Are Wrong: 12.8 ms and 6.4 ms: These imply far more than 8 cycles, inconsistent with SAR behavior. 0.05 ms (50 µs): That is only a single clock period, not 8 periods. Common Pitfalls: Forgetting that SAR uses one comparison per bit, not per code. Confusing sampling rate with clock rate; sampling rate is clock rate divided by cycles per conversion. Final Answer:0.4 ms

Question 5

GPIB (IEEE-488) cabling in automated test A crash test is monitored from 200 feet away using a GPIB test setup. A custom cable that long is fabricated to save time, and the data becomes erratic. What most likely went wrong?

Accepted Answer

Introduction / Context:The IEEE-488/GPIB bus has strict rules on total cable length and device loading to preserve signal integrity and timing margins. Violating these rules leads to reflections, attenuation, and timing errors that manifest as unreliable or “noisy” digital communication. Given Data / Assumptions: Cable length ≈ 200 feet (≈ 61 meters). Standard GPIB topology without special extenders/repeaters. Erratic, unusable data during the test. Concept / Approach:GPIB specifies maximum total length and per-device length constraints. Long, home-made cables far beyond spec cause impedance mismatches and degraded rise times. The correct solution is to shorten the cable within specifications or deploy GPIB extenders/repeaters or fiber/ethernet bridges designed for long-distance operation. Step-by-Step Solution:Recognize that 200 ft is well beyond typical GPIB cable length limits.Excess length increases capacitance/inductance and causes reflections.Therefore, a GPIB bus extender or alternative link is required. Verification / Alternative check:Vendors specify approximately tens of meters total without extenders; long-distance setups use dedicated extenders to regenerate signals and timing. Why Other Options Are Wrong: Wrong data format: Would typically cause consistent protocol errors, not distance-correlated failures. Shielding/grounding: Important, but length remains the dominant out-of-spec factor here. Extraneous signals: Possible, yet the deterministic culprit is the extreme cable length. Common Pitfalls: Assuming digital buses are immune to analog transmission line effects. Overlooking bus loading limits (number of devices and cable length). Final Answer:The GPIB cable is too long; a bus extender should be used.

Question 6

Flash (parallel-encoded) ADC sizing For converting an analog signal to 8-bit resolution using a flash (parallel-encoded) ADC, how many comparators are required?

Accepted Answer

Introduction / Context:Flash ADCs achieve extremely fast conversion by comparing the input simultaneously against many reference levels. The hardware cost scales exponentially with resolution, so computing the number of comparators is key to feasibility assessments. Given Data / Assumptions: Resolution N = 8 bits. Ideal flash topology (thermometer code) using a resistor ladder and comparators. Concept / Approach:A flash ADC requires 2^N − 1 comparators to create 2^N distinct quantization levels. Each comparator checks if Vin exceeds a specific threshold; their outputs form a thermometer code then encoded to binary. Step-by-Step Solution:Compute 2^N: 2^8 = 256 levels.Number of comparators = 2^N − 1 = 256 − 1.So, comparators required = 255. Verification / Alternative check:Check small N: for N=3, levels=8, comparators=7. Pattern holds, confirming the formula for N=8. Why Other Options Are Wrong: 127 or 128 or 256: Do not match 2^8 − 1. Common Pitfalls: Forgetting to subtract 1 from 2^N. Confusing number of levels with number of comparators. Final Answer:255

Question 7

ADC architecture selection — primary advantage What is a key advantage of a parallel-encoded (flash) analog-to-digital converter compared with other ADC types?

Accepted Answer

Introduction / Context:ADC selection balances speed, cost, resolution, and complexity. Flash (parallel-encoded) ADCs are chosen in high-speed instrumentation, oscilloscopes, and communication front ends where conversion speed is paramount. Given Data / Assumptions: Flash ADC uses 2^N − 1 comparators operating simultaneously. Trade-off: extreme speed at the cost of high component count and power. Concept / Approach:Because all thresholds are evaluated at once, conversion occurs in effectively one comparator delay plus encoder delay, making flash the fastest general ADC architecture, far outpacing SAR or integrating types at comparable resolutions. Step-by-Step Solution:Identify the dominant benefit: speed.Exclude cost/complexity as benefits; flash is typically more expensive and complex.Therefore select “Very fast conversion”. Verification / Alternative check:Vendor datasheets show flash ADCs with sampling in hundreds of MS/s to GS/s ranges, which is not practical with SAR or dual-slope converters at similar resolutions. Why Other Options Are Wrong: Less expensive / less complicated: False; comparator count makes it costly and complex. Common Pitfalls: Equating “fast” with “best” universally; noise, power, and resolution may favor other architectures. Final Answer:Very fast conversion

Question 8

Temperature transducers — linearity comparison Among common temperature sensors, which are generally the most linear over a useful range?

Accepted Answer

Introduction / Context:Different temperature sensors trade off linearity, sensitivity, cost, and range. Many industrial systems value linear response for simpler calibration and signal conditioning. Given Data / Assumptions: RTDs (typically platinum) have a near-linear resistance vs. temperature relationship over a wide span. Thermistors are highly nonlinear (steep exponential behavior) but very sensitive. Thermocouples produce low-level voltages with polynomial compensation needed. IC sensors are linear over limited ranges but often reference internal bandgaps and can drift. Concept / Approach:Linearity here refers to how closely the sensor's output follows a straight line with temperature, simplifying conversion and reducing error with simple scaling. Platinum RTDs (PT100/PT1000) are industry standards due to excellent linearity and stability. Step-by-Step Solution:Compare device physics: RTD metal resistivity vs. T ≈ linear for modest ranges.Thermistors: strong nonlinearity; need linearization.Thermocouples: polynomial relationships and cold-junction compensation required.IC sensors: linear but typically narrower range and device-specific behavior. Verification / Alternative check:Standard RTD curves (IEC 60751) show near-linear resistance changes per °C; instrumentation literature favors RTDs for linearity and stability. Why Other Options Are Wrong: Thermistors: nonlinear response. Thermocouples: nonlinear voltage output vs. temperature. IC sensors: good practicality, but RTDs are the benchmark for linearity over broad ranges. Common Pitfalls: Confusing sensitivity with linearity; thermistors are sensitive but nonlinear. Final Answer:Resistance temperature detectors

Question 9

Op-amp gain relationships Which equation correctly expresses the closed-loop voltage gain for a standard inverting operational amplifier configuration?

Accepted Answer

Introduction / Context:Operational amplifiers are the workhorse of analog design. The most common closed-loop configuration is the inverting amplifier, whose gain is set by two resistors. Recognizing the correct gain relationship is essential for sizing components and predicting circuit behavior. Given Data / Assumptions: Ideal op-amp assumptions: infinite open-loop gain, infinite input impedance at the inverting node via feedback, and zero output impedance. Standard inverting topology with Rin from source to inverting input and Rf in feedback from output to inverting input; noninverting input at ground. Concept / Approach:Under ideal assumptions, the inverting input is at virtual ground. The input current is approximately Vin / Rin and flows through Rf, generating output voltage Vout = −(Rf/Rin) * Vin. The negative sign indicates 180° phase inversion. Step-by-Step Solution:Assume virtual ground at inverting node.Compute current: I = Vin / Rin.Voltage across Rf = I * Rf; output is negative of that (due to inversion).Therefore, Vout/Vin = −Rf/Rin. Verification / Alternative check:Dimensional check and limiting cases (Rf = Rin → gain −1) agree with standard results. Why Other Options Are Wrong: Vout = Vin/Av: Relates to open-loop gain, not closed-loop. Ratios with Rout: Output resistance does not set closed-loop gain here. Common Pitfalls: Forgetting the sign inversion. Mixing open-loop and closed-loop gain formulas. Final Answer:Vout/Vin = –Rf/Rin

Question 10

Ideal op-amp traits — choosing the third property Three traits make op-amps nearly ideal for many designs: very high input impedance, very low output impedance, and which third characteristic?

Accepted Answer

Introduction / Context:Idealized operational amplifiers are defined by extreme parameters that, with feedback, yield precise, predictable closed-loop behavior. Knowing these traits helps explain why feedback linearizes and stabilizes amplifier circuits. Given Data / Assumptions: Ideal op-amp: infinite open-loop voltage gain, infinite input impedance, zero output impedance. Real op-amps approximate these properties to varying degrees. Concept / Approach:A very high open-loop voltage gain ensures that even tiny input differences drive the output such that the feedback forces the inputs to be nearly equal (virtual short). This is the cornerstone of linear closed-loop gain set by passive components. Step-by-Step Solution:Recall the three “ideals” commonly cited.High open-loop gain → accurate closed-loop gain via feedback.Therefore, select “Very high voltage gain”. Verification / Alternative check:Datasheets list open-loop gains of 10^5 to 10^6; feedback reduces sensitivity to device variations, realizing accurate closed-loop gains. Why Other Options Are Wrong: Unlimited bandwidth: No real device; gain-bandwidth product is finite. Low slew rate: Opposite of desirable; higher slew rate is preferred. Very high current gain: Not the primary idealized trait for op-amps. Common Pitfalls: Confusing current gain with voltage gain in op-amp contexts. Final Answer:Very high voltage gain

Question 11

D/A converter fundamentals — definition of resolution Which statement correctly defines the resolution of a digital-to-analog (D/A) converter?

Accepted Answer

Introduction / Context:Resolution indicates the smallest analog change a D/A converter can produce for a one-LSB digital change. It is fundamental when matching a converter to sensor accuracy and control requirements. Given Data / Assumptions: N-bit DAC has 2^N discrete output steps across full-scale range. Resolution is typically expressed as a fraction (1/2^N of full scale) or as a percentage. Concept / Approach:For an ideal N-bit DAC, the minimum output increment (1 LSB) equals full_scale / 2^N. As a fraction of full scale, resolution = 1 / 2^N, which is the reciprocal of the number of steps. (Sometimes expressed in volts: V_LSB = V_FS / 2^N.) Step-by-Step Solution:Number of steps = 2^N.Resolution (fraction of full scale) = 1 / 2^N.Hence, it is the reciprocal of the number of discrete steps. Verification / Alternative check:Example: 10-bit DAC → 1024 steps → resolution ≈ 0.0977% of full scale per LSB, matching the reciprocal definition. Why Other Options Are Wrong: Comparison between actual and expected output defines accuracy. Deviation from ideal straight line defines linearity error. Forward/reverse step resolving addresses monotonicity/hysteresis, not resolution. Common Pitfalls: Confusing resolution with accuracy or linearity. Forgetting that resolution sets granularity; accuracy tells how close outputs are to ideal. Final Answer:It is the reciprocal of the number of discrete steps in the D/A output.

Question 12

Testing an A/D with a ramp — expected oscilloscope display When a proper ramp test is applied to an A/D converter (and its reconstructed output is observed), what should the oscilloscope display look like if the A/D is functioning correctly?

Accepted Answer

Introduction / Context:A common dynamic test for A/D converters feeds a linear ramp input and observes the digitized-then-reconstructed output. This reveals missing codes, DNL/INL errors, and monotonicity issues by visual inspection of the staircase shape on an oscilloscope. Given Data / Assumptions: Input to A/D: linear voltage ramp spanning the converter range. Observation: either the A/D digital code decoded to a DAC or a scope plotting input vs. output. Ideal behavior: codes increment one by one with equal width steps. Concept / Approach:If the converter is healthy, the output will change by exactly 1 LSB per code transition, producing a staircase with uniform step heights and widths. Nonuniform steps indicate DNL/INL issues; skipped steps indicate missing codes; reversals indicate nonmonotonic behavior. Step-by-Step Solution:Apply ramp → A/D outputs successive codes.Convert codes back to analog (or XY display) → see stepwise increase.Ideal display is a uniform stairstep pattern. Verification / Alternative check:Many application notes use the ramp test and show ideal staircases to illustrate linear, monotonic converters without missing codes. Why Other Options Are Wrong: Lissajous pattern: Relates to two sinusoidal inputs, not A/D ramp testing. Straight line: Would imply continuous analog behavior, not quantized steps. Binary count display: That is a logic analyzer view, not an analog staircase on a scope. Common Pitfalls: Mistaking a smoothed staircase due to bandwidth limits as ideal; verify sampling/hold effects. Final Answer:A uniform stairstep pattern

Question 13

Diagnosing D/A converter output errors from scope display Given a D/A output that, under a code sweep, exhibits steps that occasionally reverse direction (drop instead of rise), what fault best describes this behavior?

Accepted Answer

Introduction / Context:A D/A converter should be monotonic: as the digital code increases, the analog output must never decrease. Nonmonotonic behavior breaks control loops and causes audible/visible artifacts in many systems. Given Data / Assumptions: Digital input code is swept upward sequentially. Oscilloscope shows occasional downward steps in the analog output. Connections and stimulus assumed correct unless otherwise noted. Concept / Approach:Nonmonotonic output error occurs when differential nonlinearity (DNL) is worse than −1 LSB at some transition, causing an actual decrease in output for an increasing code. This is distinct from missing codes (DNL > +1 LSB) and gain/offset errors (linear deviations). Step-by-Step Solution:Observe stair steps as code increases.Identify any downward (negative) steps.Downward steps imply nonmonotonicity → select the corresponding diagnosis. Verification / Alternative check:Datasheets specify guaranteed monotonicity up to a certain number of bits or over temperature; violation matches the observed reversal of steps. Why Other Options Are Wrong: Noisy input: Noise causes jitter, not consistent negative steps at specific codes. Scope nonlinearity: Would distort all levels, not selectively invert steps. Incorrect coding: Would reorder levels or produce missing segments, but the hallmark of nonmonotonicity is a local decrease with increasing code. Common Pitfalls: Blaming cables or probes; while they can attenuate or ring, they do not cause code-order reversals. Final Answer:The converter has a nonmonotonic output error.

Question 14

Digital-to-Analog Converter (DAC) fundamentals For a DAC with 6-bit resolution, how many distinct output voltage levels (quantization steps) are possible across its full-scale range?

Accepted Answer

Introduction / Context:A Digital-to-Analog Converter (DAC) translates a digital code into an analog voltage or current. The resolution, expressed in bits, determines how finely the full-scale analog range is divided into discrete steps. Knowing how to compute the number of output levels from the bit resolution is essential in instrumentation, audio, and control systems. Given Data / Assumptions: Resolution = 6 bits. Each additional bit doubles the number of representable codes. All codes from 0 to full-scale are assumed to be valid and monotonic. Concept / Approach: The number of unique output levels a DAC can produce equals the number of unique input codes. For an n-bit binary code, there are 2^n distinct codes. These codes map to equally spaced analog levels (ignoring nonidealities such as offset, gain error, and DNL/INL). Step-by-Step Solution: Let n = 6 bits.Number of output levels L = 2^n.Compute L = 2^6 = 64 distinct voltage steps. Verification / Alternative check: Sanity check by halving and doubling: 4 bits → 16 levels; 8 bits → 256 levels. Six bits lies between these (16 and 256), specifically at 64, which is consistent. Why Other Options Are Wrong: 6: Confuses bit count with level count. 16: Corresponds to 4 bits, not 6. 32: Corresponds to 5 bits, not 6. Common Pitfalls: Mixing up levels and steps size. The number of levels is 2^n, while the step size depends on full-scale range / (2^n − 1). Assuming non-binary coding. Standard binary-weighted DACs still yield 2^n levels regardless of coding scheme used upstream. Final Answer: 64

Question 15

Counter-ramp ADC architecture If the same analog signal is digitized to 8-bit resolution using a counter-ramp (integrating) ADC, how many comparator circuits are required in the converter hardware?

Accepted Answer

Introduction / Context:Different ADC architectures trade off speed, complexity, and hardware cost. The counter-ramp (or digital ramp) ADC uses a simple structure compared with flash ADCs. Understanding how many comparators are needed helps in estimating silicon area, power, and cost. Given Data / Assumptions: Resolution = 8 bits. Architecture = counter-ramp (digital ramp) ADC. Reference DAC and a single comparator are typical in this topology. Concept / Approach: In a counter-ramp ADC, a binary counter drives a DAC to generate a rising staircase. A single comparator compares the DAC output with the analog input. When the DAC output equals or just exceeds the input, the comparator stops the counter, and the counter value is the digital result. Unlike flash ADCs, which require 2^n − 1 comparators, counter-ramp ADCs require only one comparator regardless of resolution. Step-by-Step Solution: Identify architecture: counter-ramp.Hardware core = 1 DAC + 1 comparator + counter + control logic.Therefore, number of comparators required = 1. Verification / Alternative check: Compare with flash ADC: for 8 bits, flash needs 2^8 − 1 = 255 comparators. Successive-approximation ADCs also use one comparator. The single-comparator result aligns with established architectures. Why Other Options Are Wrong: 8, 127, 255: These reflect multi-comparator designs like flash ADC; not applicable to counter-ramp. Common Pitfalls: Confusing counter-ramp with flash or SAR and assuming comparator count scales with 2^n. Final Answer: 1

Question 16

Terminology in mixed-signal systems The process by which a computer system acquires and digitizes analog signals from sensors or instruments is called:

Accepted Answer

Introduction / Context:When interfacing the physical world with digital systems, we must sample, hold, convert, and record analog phenomena. The umbrella term for this end-to-end process—from sensor to usable digital data—is important in instrumentation, IoT, and control engineering. Given Data / Assumptions: The computer receives data from sensors via analog front-ends. Conversion to digital typically involves S/H, ADC, and buffering. The question asks for the proper term describing the overall process. Concept / Approach: Data acquisition refers to sampling analog signals, converting them to digital, and storing/streaming them for processing. It includes signal conditioning, timing, and synchronization. Terms like monotonicity and resolution are specifications of converters, not the process name. Step-by-Step Solution: Identify the scope: end-to-end capture of analog data → digital form.Match to standard terminology → “data acquisition.”Select the corresponding option. Verification / Alternative check: Industry acronyms such as DAQ (Data Acquisition) systems and cards confirm the accepted naming of this workflow. Why Other Options Are Wrong: Monotonicity: property of DAC/ADC transfer that output never reverses direction for increasing code. Analog resolution: step size or LSB definition; not a process. Systematic digital conversion: not a standard term of art. Common Pitfalls: Using component specifications (resolution, linearity) as process names. Final Answer: data acquisition

Question 17

Understanding D/A converter resolution In DAC specifications, the resolution is best defined as which of the following?

Accepted Answer

Introduction / Context:Resolution is a core DAC specification that determines the smallest change in output corresponding to a 1-LSB code change. Distinguishing resolution from accuracy and linearity helps engineers choose the right converter for a given measurement or control task. Given Data / Assumptions: DAC output range is divided into discrete steps by its bit resolution. Ideal DACs have evenly spaced levels from zero to full scale. Terminology like accuracy and linearity describe different error behaviors. Concept / Approach: For an n-bit DAC, there are 2^n discrete output codes. The resolution (as a fraction of full scale) is 1 / (2^n − 1) for step size or often approximated by 1 / 2^n across the full range. In words, it is the reciprocal of the number of output steps. Accuracy and linearity quantify how close the actual outputs are to the ideal levels, not the granularity of steps. Step-by-Step Solution: Identify the definition sought → size of the smallest output increment relative to full scale.Express as a fraction → approximately 1 / 2^n, i.e., reciprocal of number of levels.Therefore, the correct statement is that resolution equals the reciprocal of the number of discrete steps. Verification / Alternative check: Example: a 10-bit DAC has 1024 levels; resolution ≈ 1/1024 of full scale per LSB, which matches the reciprocal relationship. Why Other Options Are Wrong: Option A: describes accuracy (comparison of actual vs expected). Option C: describes integral nonlinearity (INL). Option D: loosely alludes to differential nonlinearity/hysteresis, not the resolution definition. Common Pitfalls: Equating resolution with accuracy; high resolution does not guarantee high accuracy without proper calibration and linearity. Final Answer: the reciprocal of the number of discrete steps in the D/A output

Question 18

Actuators in measurement and control In mechatronics and industrial control, an actuator is usually a device that:

Accepted Answer

Introduction / Context:Sensing and actuation are complementary functions in automation. Sensors measure the physical world, while actuators impose change upon it. Correctly identifying actuator roles helps in system partitioning and component selection for robotics, HVAC, automotive, and process control. Given Data / Assumptions: We are discussing typical actuator behavior (motors, valves, solenoids, heaters). System includes sensors, controllers, and actuators. Data conversion tasks are handled by ADCs/DACs and controllers, not actuators. Concept / Approach: An actuator accepts a command (often electrical) and produces a change in a physical variable such as position, flow, torque, or temperature. In contrast, a transducer like a sensor converts a physical variable into an electrical signal. Data processing/storage is the job of controllers or computers. Step-by-Step Solution: Identify role: device that exerts influence on the environment.Map examples: motor controls position/speed; valve controls flow/pressure; heater controls temperature.Therefore, the definition that best fits is “controls a physical variable.” Verification / Alternative check: Review standard block diagrams: Sensor → ADC → Controller → DAC/Driver → Actuator → Plant; the actuator is clearly the element applying force or change to the plant. Why Other Options Are Wrong: Converts analog to digital: that is an ADC task. Stores/processes digital data: that is a controller/computer function. Converts physical to electrical: that is a sensor/transducer role. Common Pitfalls: Labeling motor drivers or DACs themselves as actuators; they are part of the actuation chain but not the mechanical/physical output device. Final Answer: controls a physical variable.

Question 19

Purpose of sample-and-hold (S/H) circuits in ADC systems In an A/D conversion system, sample-and-hold circuits are primarily designed to do what during the conversion interval?

Accepted Answer

Introduction / Context:Real-world analog signals can vary while an ADC is converting. Without a stable input, the ADC may digitize a moving target, causing conversion errors. Sample-and-hold (S/H) circuits mitigate this by freezing the input signal level during the critical conversion window. Given Data / Assumptions: An ADC requires a stable input during quantization. S/H provides two phases: sample (track) and hold. Comparator thresholds and counters are internal to specific architectures and are not the object held by the S/H block. Concept / Approach: The S/H captures the instantaneous value of the analog input at the sampling instant and holds it constant while the ADC performs its conversions (especially important in SAR and multiplexed systems). This ensures conversion accuracy matching the rated resolution and timing. Step-by-Step Solution: Identify the varying quantity → the analog input signal.Apply S/H action → hold input constant during conversion.Therefore, the function is to stabilize the input analog signal during the conversion process. Verification / Alternative check: Observe that counter-ramp, SAR, and pipeline ADC datasheets commonly include a front-end S/H or track-and-hold, confirming the role described. Why Other Options Are Wrong: Holding a binary counter output is architecture-specific and not the function of S/H. Comparator threshold stabilization is not the role of S/H. Holding a DAC staircase is not typical; the S/H is applied at the input of the ADC. Common Pitfalls: Confusing S/H with zero-order hold used in DAC reconstruction; the purpose here is input stability for ADCs. Final Answer: stabilize the input analog signal during the conversion process

Question 20

ADC architecture comparison What is the main advantage of a successive-approximation (SAR) A/D converter compared with a counter-ramp A/D converter of the same resolution?

Accepted Answer

Introduction / Context:ADC selection is often driven by conversion speed versus complexity. Successive-approximation (SAR) and counter-ramp ADCs are classic architectures with very different time behaviors for a given resolution, making this comparison fundamental in system design. Given Data / Assumptions: Same resolution for both converters (e.g., 8–16 bits). Counter-ramp conversion time grows with input magnitude and can approach full-scale counts. SAR conversion time is deterministic, roughly proportional to the number of bits (about n comparison steps). Concept / Approach: Counter-ramp ADCs count up until the DAC output meets the analog input, so worst-case time is long (near full-scale). SAR ADCs perform a binary search using one comparator and an internal DAC; the conversion completes in about n steps independent of input magnitude, giving faster and deterministic timing. Step-by-Step Solution: Map time behavior: counter-ramp → variable and potentially long; SAR → fixed and short (≈ n steps).Therefore, SAR has the advantage of shorter conversion time. Verification / Alternative check: Typical datasheets show microsecond-level SAR conversions versus far longer worst-case counter-ramp times for the same technology node and resolution. Why Other Options Are Wrong: More/less complex circuitry: both use moderate complexity; speed advantage is the key distinguishing factor. Longer time: opposite of the SAR benefit. Common Pitfalls: Assuming architecture speed is dominated only by comparator speed; algorithmic step count is decisive here. Final Answer: shorter conversion time

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