Question 1

Practical resolution limit of a binary-weighted resistor DAC: Due to resistor ratio spread and switch accuracy, a binary-weighted resistor DAC is typically practical up to approximately how many bits of resolution?

Accepted Answer

Introduction / Context:There are two classic DAC core topologies: binary-weighted resistor DACs and R–2R ladders. While binary-weighted designs are conceptually simple, they demand precise resistor ratios that become increasingly difficult to realize as resolution increases.Given Data / Assumptions:Ideal binary-weighted DAC requires exact 1R, 2R, 4R, 8R, … ratios.Real components have tolerances and temperature coefficients.Switch on-resistance and parasitics disturb higher-order bit accuracy.Concept / Approach:Each additional bit doubles the resistor ratio range. By 8 bits, the largest/smallest resistor differ by 128:1. Maintaining accurate ratios across that span with discrete parts or even on-chip passive elements becomes challenging and expensive. Errors lead to DNL/INL problems and potential non-monotonic behavior. Thus, practical binary-weighted DACs rarely exceed about 8 bits; for higher resolution, the R–2R ladder is preferred because it uses only two resistor values, easing matching requirements.Step-by-Step Solution:List required values up to N bits: R, 2R, 4R, ... , 2^(N−1)R.Note ratio span at N=8: 2^7 = 128:1 between MSB and LSB resistors.Consider tolerance/temperature drift and switch on-resistance impact larger for small resistors.Conclude practical limit ≈ 8 bits before DNL/INL degrade.Verification / Alternative check:Historical practice: discrete binary-weighted DACs (audio/motion control) top out near 8 bits; higher-resolution DAC ICs predominantly use R–2R or segmented architectures.Why Other Options Are Wrong:10 bits: Possible only with very tight matching/trim, not “practical” broadly.2 or 4 bits: Undersell the feasible range; common binary-weighted designs exceed this.Common Pitfalls:Assuming “more bits” just means adding more resistors; ignoring that resistor and switch errors scale unfavorably with bit count in this topology.Final Answer:8 bits

Question 2

Flash (simultaneous) ADC trade-off: What is the primary disadvantage of the simultaneous analog-to-digital converter (flash ADC) architecture?

Accepted Answer

Introduction / Context:A flash, or simultaneous, analog-to-digital converter achieves extremely high conversion speed by comparing the input signal against many reference thresholds at the same instant. This design choice creates a well-known trade-off between speed and hardware complexity. The question asks you to identify the core disadvantage that limits flash ADC resolution and drives up silicon area and power.Given Data / Assumptions:A flash ADC with n-bit resolution requires distinct threshold levels spanning the full-scale input range.Each threshold is implemented with a dedicated comparator and a resistor ladder network.The encoder converts a thermometer-style comparator output into binary.Concept / Approach:The comparator count in a flash ADC grows exponentially with resolution. Specifically, an ideal n-bit flash needs 2^n − 1 comparators. This directly impacts die area, input capacitance, power consumption, offset trimming requirements, and layout complexity. Because of this scaling, practical flash converters typically target modest resolutions (for example, 6–8 bits) where the comparator count remains manageable, while still delivering exceptional sampling rates.Step-by-Step Solution:Relate bits to comparators: N_cmp = 2^n − 1.Estimate growth: moving from 6 bits (63 comparators) to 8 bits (255 comparators) quadruples the array.Infer consequences: more area and power; tighter matching and calibration challenges.Verification / Alternative check:Survey architectures across ADC families: SAR and pipeline avoid exponential comparator growth by making sequential or staged decisions, trading some speed for lower hardware complexity. This confirms that comparator count is the flash ADC bottleneck.Why Other Options Are Wrong:Requires simultaneous input application: The input is a single analog node fanned out, not separate inputs that must be applied simultaneously.Long conversion time: Flash ADCs are the fastest; conversion time is actually their strength.Large number of output lines: Encoders compact thermometer outputs; output pins are not the limiting factor.Common Pitfalls:Confusing digital output bus width with internal comparator count; assuming speed is a disadvantage rather than an advantage for flash designs.Final Answer:the large number of comparators required to represent a reasonable-sized binary number

Question 3

Feeding multiple analog sources to one ADC: When several analog inputs need conversion by a single converter, which technique is typically used before the ADC?

Accepted Answer

Introduction / Context:Systems frequently must digitize multiple sensor or signal channels with one analog-to-digital converter to save cost and board space. A common front-end strategy selects among inputs rapidly, presenting one signal at a time to the ADC. This question probes the correct term for that selection method.Given Data / Assumptions:There are several analog sources but only one ADC input channel available.Channel selection must be electronic, fast, and repeatable.The ADC can only sample one input at a time.Concept / Approach:The proper technique is multiplexing. An analog multiplexer (often called an analog switch) routes one of many input signals to a single output line under digital control. The ADC then converts that selected signal. Timing is managed so that the selected channel settles within the ADC’s acquisition window before sampling begins.Step-by-Step Solution:Place an analog multiplexer ahead of the ADC input.Use control lines to select channel n, wait for settling, then sample.Repeat for other channels on a schedule to obtain time-multiplexed conversions.Verification / Alternative check:Reference data-acquisition front ends: “MUX + buffer + S/H + ADC” is a standard chain used in multichannel designs, confirming that multiplexing is the go-to approach.Why Other Options Are Wrong:Demultiplexing: The reverse operation (one input, multiple outputs), not what we need here.R/2R: Refers to a DAC ladder network, unrelated to selecting among inputs.Comparator: A building block for ADCs, not a channel-selection method.Common Pitfalls:Ignoring settling time and source impedance when switching channels; insufficient settling can cause crosstalk or conversion error.Final Answer:multiplexing

Question 4

DAC behavior definition: A digital-to-analog converter is said to be ________ if its analog output never decreases when the binary input code increments to the next value.

Accepted Answer

Introduction / Context:In precision control and measurement systems, a fundamental requirement is that a DAC’s output behaves predictably as the digital input code increases. The formal property that captures this is called monotonicity. Knowing this term helps engineers specify converters correctly for closed-loop applications.Given Data / Assumptions:Input codes increase in standard binary sequence.We consider ideal static behavior for the definition (ignoring transient glitches).“Never decreases” refers to the final settled output after each code step.Concept / Approach:A DAC is monotonic if each increment in code results in an output that is greater than or equal to the previous output. This property ensures no “code reversals,” where a higher code produces a lower output, which can destabilize control loops and degrade audio or instrumentation quality. Monotonicity is closely related to differential nonlinearity (DNL); a DAC with DNL greater than −1 LSB is guaranteed monotonic.Step-by-Step Solution:Define behavior: for any code k, Output(k+1) ≥ Output(k).Connect to DNL: DNL ≥ −1 LSB implies no negative steps, hence monotonic.Conclude the correct term for “never decreases with increasing code” is “monotonic.”Verification / Alternative check:Datasheets often state “monotonic to n bits,” indicating guaranteed adherence to this property over the specified code range.Why Other Options Are Wrong:Self adjusting: Not a standard DAC property.Accurate: Accuracy refers to closeness to ideal; monotonicity is about order preservation.Broken: Colloquial and undefined; not a formal specification.Common Pitfalls:Confusing monotonicity with linearity; a DAC can be monotonic yet have significant INL.Final Answer:monotonic

Question 5

Output polarity range: Which class of DACs can generate both positive and negative analog output values (about a defined zero level)?

Accepted Answer

Introduction / Context:Some applications require signals that swing around a zero reference, such as audio waveforms or servo commands. DACs designed for such use must support both positive and negative outputs. The correct terminology distinguishes these from unipolar-only devices that output one polarity relative to ground.Given Data / Assumptions:We consider the DAC’s native output range, not a later level-shifting stage.A defined midscale corresponds to approximately zero volts in a bipolar configuration.Reference and amplifier networks are arranged to support two-polarity swing.Concept / Approach:A bipolar DAC or bipolar output configuration can produce both positive and negative voltages with respect to ground (or another reference), typically using dual supplies or level-shifting around a midscale reference. Unipolar DACs output from zero to a positive full-scale (or zero to a negative full-scale) and cannot cross zero without added analog conditioning.Step-by-Step Solution:Identify requirement: output must cross zero and swing both ways.Match term: “bipolar” specifically denotes two polarities.Select the answer “Bipolar.”Verification / Alternative check:Datasheets specify ranges like “±10 V bipolar” versus “0 to 10 V unipolar,” confirming the terminology used in practice.Why Other Options Are Wrong:Tristate: Refers to digital output high-impedance states, not analog polarity.Double: Not a standard DAC range descriptor.Unilateral: Not a conventional term for DAC ranges; unipolar is the typical counterpart to bipolar.Common Pitfalls:Assuming any DAC can be made bipolar without considering headroom, references, and amplifier rails.Final Answer:Bipolar

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