Question 1

Definition checkpoint: A device that converts an analog input quantity into a digital output code is called a(n) ________.

Accepted Answer

Introduction / Context: Signal-chain terminology must be precise: choosing the right component depends on knowing whether you need analog-to-digital (ADC) or digital-to-analog (DAC) conversion, and recognizing subclasses such as flash, SAR, sigma-delta, and pipeline. Given Data / Assumptions: Input is analog (voltage/current/time-varying). Output is digital (coded value). We seek the generic device name. Concept / Approach: An analog-to-digital converter (ADC) samples and quantizes an analog signal into a digital number. A “flash converter” is a specific ADC architecture. A DAC performs the inverse operation (digital to analog). “Bipolar converter” is not the generic term for A/D conversion (it can mean bipolar input handling, not conversion direction). Step-by-Step Solution: 1) Map direction: analog → digital implies ADC.2) Exclude inverse devices: DAC is digital → analog.3) Recognize flash as a subtype of ADC, not the generic name.4) Conclude the correct term is ADC. Verification / Alternative check: Any data converter catalog groups flash, SAR, sigma-delta, pipeline under the ADC category, confirming the generic terminology. Why Other Options Are Wrong: DAC converts the other way. Flash is only one ADC type. Bipolar converter does not denote A/D conversion generically. Common Pitfalls: Using architecture names (flash) when a broad category (ADC) is requested; mixing up conversion directions. Final Answer: ADC

Question 2

Counter (digital-ramp) ADC scaling: For a counter-type (digital-ramp) ADC, how does the worst-case conversion time change when you add one more bit of resolution (increase N by 1)? Choose the most accurate trend.

Accepted Answer

Introduction / Context: In a counter-type (digital-ramp) ADC, a binary counter drives a DAC. The system increases the count until the DAC output just exceeds the analog input; the count at that moment is latched as the conversion result. This architecture’s conversion time depends on how many DAC codes must be tried sequentially. Given Data / Assumptions: N-bit resolution; codes range from 0 to 2^N − 1. Clock period is fixed; one code step per clock. Worst case occurs when input is near full-scale, requiring nearly all counts. Concept / Approach: Worst-case conversion time is proportional to the number of codes to test. For N bits, that is approximately 2^N clock periods. Increasing resolution by one bit doubles the number of possible counts (2^(N+1) vs 2^N), so the worst-case time doubles. Average time also scales proportionally, though exact factors depend on input distribution and start-from-zero or tracking variants. Step-by-Step Solution: 1) Codes to test (worst case) ≈ 2^N.2) Conversion time T_worst ≈ 2^N * Tclk.3) Increase N → N + 1 → T_worst(new) ≈ 2^(N+1) * Tclk.4) Therefore, T_worst(new) / T_worst(old) ≈ 2 → time doubles. Verification / Alternative check: Compare 8-bit vs 9-bit: 256 vs 512 counts in the worst case; time per conversion doubles at the same clock. Why Other Options Are Wrong: Tripling is unsupported by the code-count relationship. Decrease options contradict the monotonic increase of code count with more bits. Common Pitfalls: Confusing counter-type with SAR (which scales ~linearly with N comparisons, not exponentially with 2^N codes); forgetting clock-rate changes can mask the doubling if the system clocks faster. Final Answer: doubles

Question 3

Stairstep-ramp ADC (4-bit) — With clock frequency = 100 kHz (period = 10 microseconds), full-scale = 10 V, and an input of 6 V applied, estimate the conversion time for the counter/stairstep process (time to reach or exceed the input level).

Accepted Answer

Introduction / Context: A stairstep-ramp (counter-type) analog-to-digital converter generates a digital count from 0 upward while a DAC creates a corresponding staircase. A comparator stops the count when the DAC staircase reaches the analog input. The conversion time therefore depends on the input amplitude (larger inputs take more steps) and the clock rate (how fast steps occur). Given Data / Assumptions: Resolution: 4 bits ⇒ 2^4 = 16 staircase steps across 0–10 V. Clock frequency: f_clk = 100 kHz ⇒ T_clk = 10 microseconds per step. Input voltage: V_in = 6 V; full-scale: V_FS = 10 V. Each step height: V_step = V_FS / 16 = 10 / 16 = 0.625 V. Concept / Approach: Conversion time is approximately the number of steps needed to reach (or just exceed) V_in multiplied by the clock period. Steps required ≈ (V_in / V_FS) * 16. Because the comparator halts on the first step at or above V_in, practical answers round to the nearest whole step based on implementation specifics. Step-by-Step Solution: Compute steps: steps ≈ (6 / 10) * 16 = 9.6 ≈ about 10 steps (implementation dependent).Time per step: T_clk = 1 / 100 kHz = 10 microseconds.Estimated conversion time: 9–10 steps * 10 microseconds ≈ 90–100 microseconds. Verification / Alternative check: Maximum conversion time occurs at full-scale: 16 steps * 10 microseconds = 160 microseconds (matches the full-scale limit). Why Other Options Are Wrong: 10 microseconds: Only one step; far less than the ~9–10 steps needed.160 microseconds: That is the worst case at full-scale (10 V), not at 6 V.6250 seconds: Physically unreasonable for these parameters. Common Pitfalls: Forgetting that counter-type ADC time varies with V_in, not fixed.Confusing step height with step time. Final Answer: 90 microseconds

Question 4

Stabilizing A/D conversion — To keep the analog input constant while the ADC is converting, which circuit should be used?

Accepted Answer

Introduction / Context: During an A/D conversion, many architectures require a stable input over the conversion interval. If the source is moving (sensor drift, mains ripple, or multiplexed channels), the ADC may sample inconsistent values across its internal phases unless the signal is briefly “frozen.” Given Data / Assumptions: We need to hold the analog voltage constant for microseconds to milliseconds. The ADC may be successive-approximation, integrating, or sigma-delta with defined sampling instants. Source impedance may be high, necessitating buffering. Concept / Approach: A sample-and-hold (S/H) circuit samples the input onto a capacitor through a switch, then opens the switch, isolating the capacitor to hold the voltage while the ADC processes. A buffer amplifier with low leakage minimizes droop, preserving accuracy throughout conversion. Step-by-Step Solution: Place S/H before ADC input.On sample command, close the switch to charge the hold capacitor to the input voltage.Open the switch to hold the voltage constant while the ADC converts. Verification / Alternative check: Datasheets of SAR ADCs specify acquisition and hold times; S/H meets these requirements. Why Other Options Are Wrong: op-amp comparator: Compares two voltages; does not hold a level.NPN amp: A generic amplifier stage without hold functionality.current loop: Refers to a transmission scheme, not voltage holding. Common Pitfalls: Using too small a hold capacitor, causing excessive droop.Ignoring source impedance and switch on-resistance during acquisition. Final Answer: sample-and-hold circuit

Question 5

Terminology — The overall procedure of converting analog data to digital form and moving it into a computer’s memory is called what?

Accepted Answer

Introduction / Context: Many systems must sense real-world analog variables (temperature, sound, vibration), convert them to digital samples, and store or process them in a computer. The umbrella term for this end-to-end process is important vocabulary in embedded and test instrumentation domains. Given Data / Assumptions: Analog signals are captured via sensors and conditioning circuits. Conversion to digital occurs via ADCs. Data is then transferred to memory for processing or logging. Concept / Approach: “Data acquisition” denotes the entire workflow: sensing, conditioning, sampling, quantization, and transfer to storage or CPU. Individual actions like “sampling” or “multiplexing” are sub-steps and do not by themselves describe the complete process. Step-by-Step Solution: Select sensor(s) and condition the signal (gain, level shift, filter).Digitize with an ADC at appropriate sample rate and resolution.Move digitized data into memory via DMA or CPU for analysis. Verification / Alternative check: Textbooks and DAQ hardware manuals define “data acquisition” as the integrated process from sensor to digital memory. Why Other Options Are Wrong: sampling: A step within data acquisition, not the whole workflow.multiplexing: Channel selection technique; not the complete process.prescaling: Frequency/level division step; again, only a subcomponent. Common Pitfalls: Using “sampling” as a synonym for the entire DAQ chain.Ignoring conditioning and transfer logistics when planning DAQ. Final Answer: data acquisition

Question 6

Architectures — A simultaneous A/D converter (all comparators acting at once) is also known by which common name?

Accepted Answer

Introduction / Context: ADC architectures vary in speed and complexity. The fastest class compares the input to many thresholds simultaneously using a bank of comparators and a priority encoder. Knowing the common names aids datasheet reading and part selection. Given Data / Assumptions: “Simultaneous” means all comparisons occur in parallel. Resolution is typically modest (e.g., 6–8 bits) due to comparator count scaling. Emphasis is on ultra-low latency. Concept / Approach: The parallel-comparator design is widely called a “flash” ADC because the conversion completes in a few gate delays, effectively in a flash, instead of iterating bit decisions sequentially like SAR or integrating converters. Step-by-Step Solution: Split the reference into 2^N − 1 thresholds via a resistor ladder.Compare input against all thresholds in parallel comparators.Encode the thermometer output into an N-bit binary code. Verification / Alternative check: Texts and vendors consistently use “flash ADC” for this architecture. Why Other Options Are Wrong: synchronous / asynchronous: Refer to clocking, not this architecture’s defining trait.comparator: A component inside an ADC; not the architecture’s name. Common Pitfalls: Assuming “flash” implies optical; it refers to speed. Final Answer: flash

Question 7

Digital signal processing (DSP) — A major application area is ________ and ________ of analog-origin signals after digitization.

Accepted Answer

Introduction / Context: DSP applies mathematical operations to sampled data to enhance, analyze, or transform signals originating in the analog world. Typical aims include noise reduction, equalization, and band selection for measurement, communication, and audio applications. Given Data / Assumptions: Signals are already digitized by an ADC. We want primary use-cases, not peripheral tasks. “Conditioning” includes scaling, windowing, equalization, and normalization in the digital domain. Concept / Approach: Filtering (low-pass, high-pass, band-pass, adaptive) is central to DSP. Conditioning encompasses operations that prepare signals for subsequent analysis or control, such as gain normalization, de-trending, or resampling. Together they represent a core DSP workload. Step-by-Step Solution: Sample the analog signal with sufficient rate and resolution.Apply digital filters to remove noise or isolate bands.Perform conditioning (scaling, offset correction, windowing) prior to feature extraction or control. Verification / Alternative check: Standard DSP curricula emphasize filtering and conditioning as first-line treatments of acquired data. Why Other Options Are Wrong: sending, receiving: Communication tasks are broader; core DSP still centers on filtering/conditioning.digitizing, weighting: Digitizing is pre-DSP (ADC); “weighting” is too narrow.leveling, translating: Vague and not representative of the main workload. Common Pitfalls: Equating DSP solely with Fourier transforms; many tasks are time-domain conditioning. Final Answer: filtering, conditioning

Question 8

ADC fundamentals — What is the proper type of input presented to an analog-to-digital converter?

Accepted Answer

Introduction / Context: An analog-to-digital converter (ADC) senses an analog quantity and outputs a digital representation. Understanding which signals belong on the ADC input versus its digital interface prevents wiring and specification mistakes. Given Data / Assumptions: Most ADCs measure analog voltage; some measure current via shunts but internally sense voltage. ADCs often require a separate digital clock and control lines, but these are not the “input quantity” being converted. Outputs are digital words or serial bitstreams. Concept / Approach: The convertible input is an analog voltage (or a voltage proportional to current). The ADC uses sampling circuits and comparators to map that voltage to a numeric code. Digital clocks and numbers relate to timing and results, not to the measured quantity. Step-by-Step Solution: Present the analog voltage within the specified common-mode and range.Provide clock/control on separate pins as required by the interface.Read the converted binary code from the ADC’s digital outputs. Verification / Alternative check: ADC datasheets specify input range and impedance for analog pins; clocks and codes appear only on digital interface pins. Why Other Options Are Wrong: a clock pulse: Needed for timing but not the quantity being converted.a binary number: That is the ADC’s output, not its measured input.any of the above: Overly broad and incorrect for the measured quantity. Common Pitfalls: Driving beyond allowable input range or without proper conditioning. Final Answer: a voltage level

Question 9

DAC behavior — The requirement that increasing (or decreasing) the digital code by one step causes exactly one corresponding step change at the output is called what?

Accepted Answer

Introduction / Context: When converting digital codes to analog signals, a key quality is whether the output moves predictably with each code step. Control systems and audio applications especially require that one code increment never produces a backward or erratic jump in the output. Given Data / Assumptions: We are discussing a DAC operating over successive codes. Focus is on the relationship between adjacent codes. Ignore absolute gain/offset errors for this definition. Concept / Approach: Monotonicity means the output never decreases when the input code increases (and never increases when the code decreases). A stricter interpretation in many specs is that each single-code change results in exactly one step in the correct direction with no reversals. Missing codes or large DNL errors can break monotonicity. Step-by-Step Solution: Consider adjacent codes k and k+1.A monotonic DAC guarantees V_out[k+1] ≥ V_out[k] for an increasing sequence.Design goal: DNL ≤ 1 LSB ensures no missing codes and preserves monotonicity. Verification / Alternative check: Datasheets list monotonicity and DNL; monotonicity is often guaranteed over temperature for precision DACs. Why Other Options Are Wrong: resolution: Smallest code step size (LSB), not the behavior of steps.linearity: Deviation from an ideal straight line (INL), not step-by-step guarantee.accuracy: Overall closeness to ideal value; broader than step behavior. Common Pitfalls: Confusing monotonicity with linearity; a DAC can be monotonic yet non-linear. Final Answer: monotonicity

Question 10

Binary-weighted DAC — In a classic binary-weighted-resistor DAC, the least significant bit (LSB) input connects to which resistor value?

Accepted Answer

Introduction / Context: Binary-weighted DACs implement bit weights using resistors in powers of two (R, 2R, 4R, 8R, ...). The mapping of each bit to a resistor value determines the contribution of that bit to the output current or voltage. Given Data / Assumptions: Most significant bit (MSB) must contribute the largest weight. Smaller resistance in a current-summing DAC yields more current (greater weight), all else equal. Thus resistor magnitude is inversely related to bit weight. Concept / Approach: To realize binary weighting, the MSB is tied to the smallest resistor (highest weight). Conversely, the least significant bit is connected to the largest resistor (lowest weight). This ensures that each less significant bit contributes half the current (or voltage) of the previous bit. Step-by-Step Solution: Assign MSB → smallest resistor (weight = 1/2 of full-scale step basis inverted by R).Assign LSB → largest resistor (1/2^N of MSB weight).Confirm summing network yields binary-weighted output. Verification / Alternative check: Standard DAC texts show LSB on the largest resistor for binary-weighted designs. Why Other Options Are Wrong: connects to the smallest resistor: That would make the LSB too large in weight.supplies the least voltage: Varies by topology; the defining feature is resistor value/weighting.connects to a 1 kΩ resistor: Arbitrary value; depends on design scale. Common Pitfalls: Confusing binary-weighted DACs with R/2R ladders, which use only two resistor values. Final Answer: connects to the largest resistor

Question 11

Clock usage — Which ADC architecture does not require a clock because it performs no sequential timing or bit-by-bit decision process?

Accepted Answer

Introduction / Context: Many ADCs rely on timing sequences (e.g., SAR bit trials, integrating cycles), which require clock signals. However, one architecture works by making all comparisons in parallel with no sequential steps, and thus no conversion clock is strictly required for its core decision. Given Data / Assumptions: We focus on the core conversion mechanism, not on digital interface housekeeping. Parallel comparison against multiple thresholds is used. An encoder converts thermometer code to binary. Concept / Approach: A flash ADC employs a bank of comparators referencing a resistor ladder. The output is determined as soon as comparator outputs settle; no iterative clocked sequence is needed. While practical systems may still clock the readout or pipeline stages, the essential conversion itself is asynchronous. Step-by-Step Solution: Input is applied to all comparators simultaneously.Comparators resolve almost immediately to a thermometer code.Priority encoding produces the binary output. Verification / Alternative check: Architecture diagrams show no SAR logic or integration cycles that would mandate a clock. Why Other Options Are Wrong: Actuator: Not an ADC type.Dual: Likely refers to dual-slope ADCs, which require precise timing.Bipolar: Refers to signal polarity or device technology, not an ADC architecture. Common Pitfalls: Confusing the lack of conversion clock with entirely clockless devices; readout logic may still be clocked. Final Answer: Flash

Question 12

Circuit identification — The shown network (weighted currents summed via equal 2R branches and R returns) corresponds to which classic data-converter circuit?

Accepted Answer

Introduction / Context: Two common DAC realizations are the binary-weighted-resistor DAC and the R/2R ladder DAC. Textbook schematics often show a repetitive ladder using only two resistor values (R and 2R), with digital switches steering nodes either to a reference or ground. Recognizing this pattern is essential in converter identification questions, even when a figure is summarized in text. Given Data / Assumptions: The circuit shows repeating R–2R sections feeding a summing node. Each bit controls a switch connecting a ladder tap to V_ref or ground. An op-amp may be used as a transimpedance stage to produce V_out. Concept / Approach: The R/2R ladder uses only two resistor values, simplifying matching and scaling. Each additional bit adds one identical section, making the design highly modular. Equal 2R branches ensure that each bit contributes a precisely halved weight relative to the next more significant bit without requiring exponentially small or large resistor values. Step-by-Step Solution: Identify the repeating R–2R sections and their taps controlled by bit switches.Note that currents from all sections sum at the output node or op-amp summing junction.Conclude that the structure is an R/2R ladder DAC, not a binary-weighted resistor network requiring many resistor values. Verification / Alternative check: Compare with binary-weighted DACs: those require R, 2R, 4R, 8R, ...; the ladder requires only R and 2R. Why Other Options Are Wrong: four-bit decoder: A logic device, not an analog converter network.binary-weighted-input DAC: Different topology using many resistor values.four-bit A/D converter: ADCs are measurement devices, not resistor ladders with output summing nodes as shown. Common Pitfalls: Assuming any ladder of resistors is an A/D; the presence of bit-controlled switches and a summing node indicates a DAC. Final Answer: R/2R ladder D/A converter

Question 13

Counter-ramp (digital-ramp) ADC principle: In a counter-ramp analog-to-digital converter, the comparator continuously compares the unknown analog input voltage against which reference signal within the conversion loop?

Accepted Answer

Introduction / Context: A counter-ramp (also called digital-ramp) ADC is one of the simplest converter architectures. It builds a staircase reference using a DAC and a counter, then uses a comparator to determine when that staircase reaches the unknown input level. Knowing exactly what the comparator is comparing clarifies how code, time, and voltage relate in this ADC type. Given Data / Assumptions: The converter contains a binary counter feeding a DAC. The DAC produces a staircase (increasing) voltage as the counter increments. A comparator senses the relationship between the analog input and the DAC output. Clock and control logic stop the count when the staircase just meets the input. Concept / Approach: The counter drives the DAC with successively larger digital codes. The DAC converts each code to an analog level, forming a staircase. The comparator continuously evaluates V_in − V_DAC. When V_DAC becomes equal to or just exceeds V_in (depending on design), the control logic stops the counter. The digital count then represents the measured value of the input. Step-by-Step Solution: Start with counter = 0; DAC output is the lowest level.On each clock, increment the counter; DAC output steps up accordingly.Comparator checks if V_in > V_DAC; if true, continue counting.When V_DAC ≥ V_in (threshold reached), stop the counter; read the count as the digital result. Verification / Alternative check: An oscilloscope view shows a staircase (DAC output) rising until it meets the static input. The instant the two match, the counter freezes—confirming that the comparator compares V_in to the DAC output, not to the raw counter value or a passive divider. Why Other Options Are Wrong: a binary number: The comparator operates on voltages, not abstract numbers. the output of a counter: The counter is digital; the comparator needs analog levels. a voltage divider network: A passive divider is not how the reference staircase is generated here; the DAC provides the reference. Common Pitfalls: Confusing the counter (digital) with the DAC (analog); assuming the comparator directly “reads” the counter value; overlooking that resolution and conversion time depend on clock rate and full-scale steps. Final Answer: the output of a DAC

Question 14

Stopping condition in a counter-ramp ADC: A counter-ramp ADC halts counting at the exact moment when which equality condition is satisfied?

Accepted Answer

Introduction / Context: Understanding the stop condition in a counter-ramp ADC is essential to relate the final digital count to the measured analog input. This architecture converts time (the number of clock pulses counted) into amplitude by comparing a generated staircase to the unknown input. Given Data / Assumptions: ADC uses a binary counter, a DAC, and a comparator. On each clock pulse, the counter increments, raising the DAC output one LSB. Comparator monitors V_in versus V_DAC (staircase). Control logic stops the count when the reference meets the input. Concept / Approach: As the DAC output climbs in steps, the comparator output flips when V_DAC reaches (or slightly exceeds, per design) V_in. That transition triggers the logic to stop the counter. The captured count is the digital representation of the input and is proportional to the time it took to reach equality. Step-by-Step Solution: Initialize counter=0; V_DAC = 0 (or minimum level).Clock → counter increments → V_DAC rises by 1 LSB each tick.Comparator evaluates sign(V_in − V_DAC).When V_DAC ≈ V_in, comparator toggles → counter is halted → result captured. Verification / Alternative check: A timing diagram shows comparator output high until the step reaches V_in, then toggling low (or vice versa), coincident with the stop signal. The stop is not tied to a magic 5 V threshold or to hitting the maximum count unless V_in equals full scale. Why Other Options Are Wrong: Counter reaches maximum count: Only true if V_in is full-scale; not the general stop condition. Input equals 5 V / DAC equals 5 V: Arbitrary voltage; depends on reference and scaling, not a fixed 5 V. Common Pitfalls: Assuming a constant conversion time regardless of V_in; forgetting that conversion time varies with input magnitude in a counter-ramp ADC. Final Answer: the input voltage equals the DAC staircase voltage

Question 15

Tracking (servo) ADC vs. stairstep-ramp ADC: Identify the principal advantage of a tracking ADC when compared with a simple stairstep-ramp (counter-ramp) ADC.

Accepted Answer

Introduction / Context: Both tracking (servo) ADCs and stairstep-ramp ADCs use a DAC and comparator, but they differ in how the digital code evolves. A tracking ADC employs an up/down counter that continually adjusts, “tracking” the input, whereas a stairstep-ramp ADC restarts from zero for each conversion. This architectural difference affects speed and responsiveness. Given Data / Assumptions: Tracking ADC: up/down counter, adjusts code by ±1 LSB per step toward V_in. Stairstep-ramp ADC: up counter always ramps up from zero until reaching V_in. Same DAC resolution and clock rate assumed for fair comparison. Concept / Approach: The worst-case conversion time for a stairstep-ramp ADC is proportional to the code value (must count from 0 to the target). In contrast, a tracking ADC starts at the previous code and only moves as many steps as the input has changed. For slowly varying inputs, the number of steps per sample is small, yielding much faster effective conversions after the first acquisition. Step-by-Step Solution: Assume prior code equals current code → tracking ADC finishes in ~0–1 steps.For a small input change Δcodes, tracking ADC needs only |Δcodes| steps.Stairstep-ramp needs current_code steps from zero every time.Therefore, tracking is faster for typical signals that change gradually. Verification / Alternative check: Sequence diagrams show a tracking ADC dithering by ±1 LSB for constant inputs and quickly following small ramps. Counter-ramp traces restart and take longer on average, particularly for mid-scale and high-scale values. Why Other Options Are Wrong: Does not require a counter: A tracking ADC explicitly uses an up/down counter. Indicate polarity / measure positive and negative: While up/down direction reflects error polarity, that is not the key advantage cited. Common Pitfalls: Judging “speed” only by first conversion; in steady operation, tracking excels because it starts near the answer. Final Answer: it is faster

Question 16

Recognizing a converter topology from a schematic: The circuit shown (ladder of alternating R and 2R branches terminating at a summing node and an op-amp) is best identified as which of the following?

Accepted Answer

Introduction / Context: Many textbooks include images of two common DAC core topologies: the binary-weighted resistor DAC and the R–2R ladder DAC. Being able to distinguish them at a glance is a foundational skill for reading mixed-signal schematics and recognizing how switching networks generate accurate analog levels from digital codes. Given Data / Assumptions: Figure shows repeated sections of resistors with only two values, R and 2R. Each bit controls a switch that connects a ladder node to either reference or ground. Ladder converges to a summing node, commonly at an op-amp input. No explicit resistor ratios of 1:2:4:8 visible at the summing node. Concept / Approach: An R–2R ladder uses just two resistor values and forms a repetitive ladder, making it layout-friendly and tolerant of matching errors compared to large binary-weighted ratios. In contrast, a binary-weighted DAC ties bit switches to resistor values with clear 1R, 2R, 4R, 8R scaling at the summing node. The presence of repeated “R” and “2R” segments identifies an R–2R ladder DAC. Step-by-Step Solution: Scan the schematic for only two resistor values: R and 2R.Observe the repeating ladder sections feeding a single summing point.Note each bit switch steering between V_ref and ground.Conclude: R–2R ladder DAC, not a decoder or ADC. Verification / Alternative check: Compute the Thevenin equivalences of ladder segments; each bit contributes a binary-weighted current at the summing node despite uniform resistor values—characteristic of R–2R topology. Why Other Options Are Wrong: Four-bit decoder: Purely digital; no summing of analog currents. Binary-weighted-input DAC: Would show explicit 1R:2R:4R:8R resistors tied directly to the op-amp node. Four-bit A/D converter: An ADC requires a comparator array or conversion logic, not just a resistor ladder to an op-amp. Common Pitfalls: Confusing a resistor string DAC (ladder of equal resistors to a tap network) with an R–2R ladder; overlooking the alternating R and 2R pattern. Final Answer: R/2R ladder D/A converter

Question 17

Key converter term: The count of binary bits used at a DAC’s input (or produced at an ADC’s output) is referred to as which specification?

Accepted Answer

Introduction / Context: Converter datasheets list several performance metrics. Among them, the number of bits is foundational because it sets the quantization granularity, code range, and ideal step size. Correct terminology avoids confusion when sizing a converter for a given application. Given Data / Assumptions: DAC input width or ADC output width is N bits. Ideal code range is 0..(2^N − 1) for straight binary. We seek the term that names this bit width. Concept / Approach: Resolution is the smallest change discernible in the converter’s output/input, ideally one least significant bit (1 LSB) relative to full scale. The number of bits directly defines resolution as a fraction of full scale: 1 / 2^N. Accuracy, linearity, and monotonicity are different (and usually worse-case) error and behavior specifications layered atop the ideal resolution. Step-by-Step Solution: Let N = number of bits.Ideal LSB fraction = 1 / 2^N of full scale.Thus, “N” is the converter’s resolution in bits.Other specs (accuracy, linearity, monotonicity) describe deviations or properties beyond resolution. Verification / Alternative check: Typical datasheets: “Resolution: 12 bits”; “INL: ±1 LSB”; “DNL: ±0.5 LSB”; “Monotonic over temperature,” clearly separating resolution from other metrics. Why Other Options Are Wrong: Accuracy: Closeness to true value, includes gain/offset/nonlinearity errors. Linearity: INL/DNL behavior compared to a straight line. Monotonicity: Output never decreases for increasing code; not the bit count. Common Pitfalls: Assuming more bits always mean more accuracy; real accuracy depends on errors and noise, not just resolution. Final Answer: resolution

Question 18

Fixed conversion-time ADCs: Which ADC architecture has a fixed conversion time that does not depend on the magnitude of the analog input value?

Accepted Answer

Introduction / Context: ADC conversion time impacts sampling rate and latency. Some architectures take longer when the input is near one extreme; others complete in a constant number of steps regardless of the input code. Identifying which is which is crucial for real-time designs. Given Data / Assumptions: We compare common ADC types: dual-slope, counter-ramp, successive-approximation (SAR). “Fixed conversion time” means a predictable, constant number of cycles per sample. Input amplitude should not change the duration. Concept / Approach: A SAR ADC performs a binary search through all bit positions in exactly N steps for an N-bit result. The process sets MSB..LSB decisions in sequence using an internal DAC and comparator; thus conversion time is deterministic. Counter-ramp time depends on the final code (must count from zero to the target), and dual-slope includes a fixed integrate phase but a de-integrate phase that varies with input, so total time is not strictly constant with amplitude. Step-by-Step Solution: For N bits, SAR executes N comparison steps per sample.Each step takes one (or a few) clock periods → fixed total time.Counter-ramp: steps equal to code value → time varies with input.Dual-slope: de-integrate duration ∝ input → not constant overall. Verification / Alternative check: Datasheets specify “conversion time = N * t_clk” for SAR, versus “max conversion time up to full-scale” for ramp types and “measurement time set by integration window” for dual-slope with variable back-half. Why Other Options Are Wrong: Substandard/Recessive-approximation: Not standard ADC categories. Dual: Not fixed total time vs input; accuracy advantage lies elsewhere (noise rejection). Common Pitfalls: Confusing “sampling rate” with “throughput”; assuming dual-slope is fixed because its first phase is fixed—overall time still depends on input during de-integration. Final Answer: Successive-approximation

Question 19

Undersampling terminology: Sampling a signal at a rate below the Nyquist minimum produces a spurious component known as a(n) ________.

Accepted Answer

Introduction / Context: The Nyquist–Shannon sampling theorem states that to capture all information in a bandlimited signal, the sampling frequency must be strictly greater than twice the highest frequency component. Violating this condition leads to spectral overlap in the sampled domain, creating deceptive components in the reconstructed or analyzed signal. Given Data / Assumptions: Sampling at f_s < 2 * f_max. Real-world signals may not be perfectly bandlimited; anti-alias filters are used. We seek the term for the resulting artifact. Concept / Approach: When sampling below Nyquist, higher-frequency content folds back (mirrors) into lower frequencies within the baseband, producing components that were not present in the original baseband. These folded components are called aliases. Anti-aliasing filters attenuate frequencies above f_s/2 to prevent this phenomenon. Step-by-Step Solution: Define Nyquist rate: f_N = 2 * f_max.If f_s < f_N, frequency components above f_s/2 map into baseband.These mappings create false tones/components → aliases.Mitigate by low-pass filtering prior to sampling and/or increasing f_s. Verification / Alternative check: Spectrum plots show mirrored images about integer multiples of f_s; the overlapping areas in 0..f_s/2 are the aliases perceived after sampling. Why Other Options Are Wrong: Nyquist: A theorem/rate, not the artifact. Sampling frequency: A parameter, not the artifact. Basis: Unrelated; term from linear algebra or transforms. Common Pitfalls: Confusing undersampling used deliberately with bandpass signals and stringent filtering with careless undersampling that causes distortion; assuming DSP can “fix” aliasing after the fact (it cannot). Final Answer: alias

Question 20

Fastest ADC architecture: Among common converter types, which analog-to-digital converter is known for the highest conversion speed (lowest latency) at a given resolution?

Accepted Answer

Introduction / Context: ADC architectures trade off speed, power, area, and accuracy. In time-critical applications like high-speed oscilloscopes, radar front-ends, and communication receivers, the fastest conversion method is often required, even at the cost of power and silicon area. Given Data / Assumptions: Compare counter-ramp, SAR, dual-slope, and parallel (flash) ADCs. Resolution is moderate (a few to ~8 bits typical for flash). Focus on raw conversion latency per sample. Concept / Approach: A parallel (flash) ADC uses 2^N − 1 comparators in parallel to compare the input simultaneously against all threshold levels generated by a resistor ladder. A priority encoder then converts the thermometer code to binary in essentially one comparator delay plus small logic latency. No sequential steps are required, making it the fastest architecture in terms of latency. Step-by-Step Solution: Resistor ladder generates equally spaced references.All comparators evaluate the input at once.Thermometer pattern feeds a priority encoder.Output binary code appears within nanoseconds (technology-dependent). Verification / Alternative check: Flash ADC datasheets specify sub-nanosecond to low-nanosecond latencies. SAR devices require N serial decisions; counter-ramp counts through many steps; dual-slope integrates over relatively long windows for precision and noise rejection. Why Other Options Are Wrong: Counter ADC: Slow, sequential counting. Successive-approximation: Fast and popular, but still N serial steps. Dual slope: Precision over speed; conversion time is longest. Common Pitfalls: Equating throughput with latency without considering pipeline effects; overlooking power and area penalties of flash ADCs as resolution grows. Final Answer: parallel ADC

Interfacing to the Analog World Questions