Flash ADC trade-off: The main disadvantage of the flash (simultaneous) A/D converter architecture is the large number of required comparators. Evaluate this statement.

Introduction / Context:
Flash A/D converters achieve extraordinary speed by comparing the input simultaneously against many reference thresholds and encoding the result. This parallelism trades silicon area and power for speed. The question asks whether the comparator count is the principal drawback.

Given Data / Assumptions:

• n-bit flash ADC requires 2^n − 1 comparators.
• Resistor ladder generates evenly spaced thresholds.
• High-speed thermometer-to-binary encoding is included.

Concept / Approach:
Because comparator count grows exponentially with resolution, area, input capacitance, power consumption, and offset calibration complexity all increase rapidly. For example, 8 bits needs 255 comparators; 10 bits would need 1023, which is usually impractical. Hence, the overwhelming disadvantage is the large comparator array, making flash ADCs suitable for low-resolution, very-high-speed roles (e.g., 6–8 bits at hundreds of MS/s to GS/s) rather than medium/high-resolution applications.

Step-by-Step Solution:

Verification / Alternative check:
Most medium/high-resolution ADCs adopt SAR, pipeline, or sigma-delta architectures specifically to avoid exponential comparator scaling.

Why Other Options Are Wrong:

Common Pitfalls:
Assuming flash is universally best due to speed; for many applications, power and area budgets dominate.

Final Answer:
Correct