Question 1

Identifying analog quantities in measurement and control Which statement correctly characterizes an analog quantity in electronics and instrumentation?

Accepted Answer

Introduction / Context: Analog signals are ubiquitous in sensors and control systems. Distinguishing analog from digital is foundational for choosing conversion (ADC/DAC) methods, filters, and signal conditioning. Given Data / Assumptions: We compare general properties of analog versus digital signals. No special transfer function (like logarithmic) is implied for all analog signals. Concept / Approach: An analog quantity can take any value within a continuous interval (for example, 0 to 5 V, or −10 to +10 V). In contrast, digital quantities take values from a discrete set (quantized steps). While some analog systems have logarithmic responses, that is not a universal trait of “analog.” Step-by-Step Solution: Identify the defining feature: continuity of possible values.Map each option to continuous vs. discrete characteristics.Select the statement that explicitly says “continuous set of values.” Verification / Alternative check: A temperature sensor producing 0–10 V is analog because it can output infinitely many voltages in that range; a 10-bit ADC version of that signal would be discrete (1024 steps). Why Other Options Are Wrong: Discrete levels / finite steps: These are digital properties. Logarithmic response: Specific to certain analog elements (e.g., dB scales, diode I-V), not a defining characteristic. Common Pitfalls: Assuming analog implies nonlinearity; analog can be linear or nonlinear. Final Answer: It has a continuous set of values over a given range.

Question 2

Diagnosing a DAC output that is uniformly shifted Referring to the shown D/A converter output (figure referenced in the original item), what appears to be wrong, and how should the problem be corrected?

Accepted Answer

Introduction / Context: D/A converter troubleshooting often starts by distinguishing offset error (uniform vertical shift), gain error (slope error), and nonlinearity (deviation from a straight line). Knowing these signatures speeds diagnosis. Given Data / Assumptions: The staircase/ramp output is uniformly displaced from zero by a constant amount across codes. No distortion or code-dependent bowing is reported. Concept / Approach: Offset error appears as a constant shift of the entire transfer characteristic. Common causes: op-amp input offset voltage, bias currents with source impedance, or reference/bipolar offset network tolerance. Nonlinearity would show curvature or step irregularity; gain error would change slope. Step-by-Step Solution: Inspect the transfer: parallel to ideal but shifted → offset.Check for offset-trim provisions (hardware trim pin or software calibration).If the design lacks trim or the op-amp's offset is excessive, replace or choose a lower-offset amplifier. Verification / Alternative check: Measure output for code 0 and full-scale; if both are equally shifted relative to ideal, the error is offset, not slope or linearity. Why Other Options Are Wrong: Nothing wrong: A uniform shift is not ideal behavior. Nonlinearity: Would not stay parallel to the ideal line. Power supply too high: That would more likely affect headroom, clipping, or reference rails, not a consistent offset alone. Common Pitfalls: Misinterpreting a consistent shift as gain error—gain changes slope, not intercept. Final Answer: There is an offset error; if no provision is made for adjusting the offset, the op-amp may need to be changed.

Question 3

Key benefit of the R/2R ladder DAC architecture Compared with a binary-weighted-resistor DAC, what is the principal advantage of the R/2R ladder approach?

Accepted Answer

Introduction / Context: Choosing a DAC topology affects accuracy, cost, and manufacturability. The R/2R ladder dominates discrete implementations because it relaxes resistor tolerance and matching requirements. Given Data / Assumptions: Comparing R/2R ladder versus binary-weighted resistors. Equal nominal performance targets (same bit width). Concept / Approach: In a binary-weighted DAC, resistor values span wide ratios (e.g., R, 2R, 4R, 8R, …), making precision and matching difficult. The R/2R ladder instead uses only two values (R and 2R) repeatedly, greatly simplifying trimming and keeping parasitics consistent—resulting in better matching and scalability. Step-by-Step Solution: Identify what makes R/2R practical: only two resistor values.Recognize manufacturing and tolerance benefits of using just R and 2R.Select the option that states this core advantage. Verification / Alternative check: Review of typical DAC IC datasheets and textbooks consistently cites “only two resistor values” as the R/2R ladder’s major advantage. Why Other Options Are Wrong: Fewer parts: Part count is similar for a given resolution. Easier analysis: Analysis simplicity is not the primary advantage. Virtual ground eliminated: Many implementations still use an op-amp summing node at virtual ground. Common Pitfalls: Confusing lower parts variety with lower part count. Final Answer: It uses only two different resistor values.

Question 4

Output level count of a basic 4-bit DAC A basic 4-bit digital-to-analog converter can produce how many distinct output values, and are those values proportional to the binary input?

Accepted Answer

Introduction / Context: Resolution and proportionality are fundamental DAC characteristics. A 4-bit converter’s output range is quantized into a finite number of equally spaced steps proportional to the digital code. Given Data / Assumptions: Resolution N = 4 bits. Unipolar ideal DAC behavior assumed. Concept / Approach: An ideal N-bit DAC produces 2^N discrete output levels. For N = 4, there are 16 distinct values. These values are proportional to the input code, spaced by one LSB (Vref / 2^N for voltage-mode). Step-by-Step Solution: Compute levels: 2^4 = 16.Note proportionality: Vout = (Code / 2^N) * Vref (or scaled current mode).Conclude 16 proportional output levels. Verification / Alternative check: Enumerate codes 0000 through 1111 → 16 unique outputs from zero to near full-scale. Why Other Options Are Wrong: 32 values: Would require 5 bits. Not proportional: Ideal DAC outputs are proportional to the input code. Common Pitfalls: Confusing number of codes (2^N) with number of steps between codes (2^N − 1 intervals). Final Answer: 16 different values of voltage or current that are proportional to the input binary number

Question 5

Reducing quantization error in ADC systems How can quantization error be reduced in a counter-type or similar analog-to-digital converter architecture?

Accepted Answer

Introduction / Context: Quantization error arises because an ADC can only represent the input with discrete codes. Increasing resolution reduces the LSB size and therefore the quantization step error. Given Data / Assumptions: Counter-type (or similar) ADC using an internal DAC for comparison. Resolution determined by number of bits N. Concept / Approach: The LSB equals full-scale range / 2^N. Quantization error is on the order of ±0.5 LSB for an ideal converter. Increasing N increases 2^N and thus reduces LSB size and error magnitude. Both the counter and DAC must support the higher resolution. Step-by-Step Solution: Recognize quantization step ∝ 1 / 2^N.To reduce step size, increase N in both the counter and DAC.Select the option that increases resolution consistently. Verification / Alternative check: Example: doubling bits from 8 to 9 halves the LSB, halving quantization error in volts. Why Other Options Are Wrong: Decrease bits: Makes the LSB larger, increasing error. Mismatched changes: Increasing only one of counter or DAC does not improve system resolution. Common Pitfalls: Confusing quantization error with noise or linearity; increasing bits specifically addresses quantization. Final Answer: increasing the number of bits in the counter and DAC.

Question 6

Flash (simultaneous) ADC timing What is the effective conversion time characteristic of a flash analog-to-digital converter?

Accepted Answer

Introduction / Context: ADC architectures trade hardware complexity for speed. Flash ADCs are the fastest because they compare the input simultaneously against many thresholds. Given Data / Assumptions: Flash ADC (aka simultaneous, parallel) with a resistor ladder and bank of comparators. No pipeline or sequential steps are involved in the basic decision. Concept / Approach: In a flash ADC, all comparator decisions occur in parallel, so the output code reflects the input essentially continuously, changing as soon as the comparators and encoder settle (propagation delay on the order of nanoseconds for many devices). Hence, there is no distinct multi-microsecond “conversion time” like in SAR or integrating ADCs. Step-by-Step Solution: Recognize that flash uses parallel comparators.Understand that outputs update as the analog input crosses thresholds.Therefore, describe timing as effectively continuous (bounded by comparator/encoder propagation delays). Verification / Alternative check: Datasheets specify propagation delay and maximum sampling rate; there is no N-cycle conversion sequence as in SAR. Why Other Options Are Wrong: Fixed microsecond values: Those are characteristic of slower architectures and are orders of magnitude longer than flash delays. Common Pitfalls: Confusing sampling period (set by external clock) with internal conversion latency; flash conversion is parallel. Final Answer: The conversion takes place continuously.

Question 7

Names and aliases of ADC architectures A simultaneous analog-to-digital converter is also commonly called a ________ ADC.

Accepted Answer

Introduction / Context: Many ADC types have alternative names that describe their operating principle. Recognizing these aliases aids datasheet reading and system selection. Given Data / Assumptions: “Simultaneous” indicates parallel comparisons rather than sequential approximation or integration. Concept / Approach: The simultaneous ADC performs many threshold comparisons at the same time using a bank of comparators and a resistor ladder. This architecture is widely known as a flash ADC. Step-by-Step Solution: Map “simultaneous” → “flash” architecture.Select the alias that matches this principle. Verification / Alternative check: Textbooks and vendor literature consistently equate “simultaneous” with “flash.” Why Other Options Are Wrong: Synchronous/asynchronous: Describe timing relationships, not the parallel comparator structure. Comparator: A component used, not the architecture name. Common Pitfalls: Assuming “synchronous” means “simultaneous”; synchronous refers to clocking, not parallel comparisons. Final Answer: flash

Question 8

Resolution of a 12-bit DAC expressed as a percentage of full scale Calculate the ideal step size (resolution) of a 12-bit DAC as a percent of full-scale output.

Accepted Answer

Introduction / Context: Resolution specifies the smallest change in analog output corresponding to a one-LSB change in the digital input. Expressing it as a percent of full scale helps compare converters of different bit widths. Given Data / Assumptions: Ideal unipolar 12-bit DAC. Resolution (1 LSB) = full-scale range / 2^N. Concept / Approach: For N bits, the step size fraction is 1 / 2^N. As a percentage, PercentResolution = (1 / 2^N) * 100%. For N = 12, 2^12 = 4096. Step-by-Step Solution: Compute 1 / 4096 = 0.000244140625 (fraction of full scale).Convert to percent: 0.000244140625 * 100 = 0.0244140625%.Round sensibly → 0.0244%. Verification / Alternative check: Rule of thumb: each additional bit halves the percent resolution. 10-bit ≈ 0.0977%, 11-bit ≈ 0.0488%, 12-bit ≈ 0.0244%. Why Other Options Are Wrong: 0.0488%: That corresponds to 11-bit resolution (1/2048). 0.000488%: Far too small; would imply 1/204,800 of full scale. 0.0833%: About 1/1200, not a power-of-two step. Common Pitfalls: Using 2^N − 1 instead of 2^N for step size; for percent resolution, 1/2^N% is standard. Final Answer: 0.0244%

Question 9

Step size of a 6-bit ADC over a 0–7 V input range An analog signal varies from 0 V to 7 V and is digitized by a 6-bit ADC. What analog value does each 1-LSB step represent on the digital output?

Accepted Answer

Introduction / Context: Knowing the LSB size of an ADC allows quick estimation of quantization error and measurement resolution across a given input range. Given Data / Assumptions: Input span: 0 to 7 V. Resolution: 6 bits → 64 codes. Ideal mid-tread behavior assumed for step size calculation. Concept / Approach: The LSB step size for an ideal ADC is Step = Full-Scale Range / 2^N. Here, N = 6, so 2^N = 64. Step-by-Step Solution: Compute step: 7 V / 64 = 0.109375 V.Round to three decimals: ≈ 0.109 V.Therefore, each increment in the digital code corresponds to about 0.109 V of the input. Verification / Alternative check: 2^6 = 64; 0.1 V × 64 = 6.4 V, so the precise 0.109375 V step is consistent with a 7 V span. Why Other Options Are Wrong: 0.111 V: Close but not exact; it overestimates the step. 1.17 V / 0.857 V: These are far too large; they would imply minimal resolution (3–8 steps total). Common Pitfalls: Dividing by 2^N − 1 for step size; while code count is 0..63, the step size calculation uses 2^N in ideal mid-tread models. Final Answer: 0.109 V

Question 10

Counter-ramp (single-slope) ADCs: identify the key disadvantage In data-conversion systems, a counter-ramp (single-slope integrating) analog-to-digital converter counts clock pulses until the integrator output matches the input. What is the principa…

Accepted Answer

Introduction / Context: The counter-ramp (single-slope integrating) ADC converts an analog voltage by charging or discharging an integrator while a counter advances with a fixed clock. When the comparator detects equality, the count is latched as the digital result. Understanding its timing behavior reveals the main trade-off of this simple architecture. Given Data / Assumptions: Conversion is performed by a ramp/integrator driven by a constant current. Time to convert is proportional to input magnitude. A stable clock and reference are assumed. Concept / Approach: Single-slope ADC conversion time scales with the analog input and the clock period. Worst-case time occurs at or near full-scale and equals (maximum count) * (clock period). Because each conversion requires the ramp to traverse a large portion of the range, throughput is limited compared with successive-approximation (SAR) or flash ADCs. Step-by-Step Solution: Let T_clk be the clock period and N_counts the count reached for the input.Conversion time T_conv ≈ N_counts * T_clk (worst case near full scale).To improve resolution, the clock must be faster or the ramp slower; both create practical limits.Therefore, relative to SAR (≈ constant N clocks) or flash (≈ 1–2 comparator delays), single-slope is slow. Verification / Alternative check: Compare architectures: SAR needs about one clock per bit (fixed time), flash is nearly instantaneous but costly, dual-slope averages noise but still has long, fixed integration times. Single-slope is among the slowest because it measures time proportional to input level. Why Other Options Are Wrong: complex circuit: Single-slope is actually simple (integrator + comparator + counter). high cost: Parts count is low, so cost is typically modest. —: Not a meaningful technical disadvantage. Common Pitfalls: Confusing single-slope with dual-slope; dual-slope has fixed integration periods and superior noise rejection. Assuming slow speed is acceptable without considering required sampling rates. Final Answer: very slow

Question 11

D/A converter specifications: define linearity clearly In the context of a digital-to-analog converter (DAC), what is meant by “linearity”?

Accepted Answer

Introduction / Context: DAC data sheets list several static accuracy terms: resolution, offset error, gain error, integral nonlinearity (INL), and differential nonlinearity (DNL). Distinguishing these terms is essential when selecting a converter for instrumentation, audio, or control applications. Given Data / Assumptions: We consider static transfer behavior of an ideal versus a real DAC. “Linearity” here refers to the integral nonlinearity concept. Concept / Approach: Ideally, a DAC’s transfer function is a straight line relating code to output. Real devices deviate from this line due to resistor mismatch, current-source errors, and layout effects. Linearity quantifies the worst-case deviation of actual code points from a best-fit or endpoint straight line, independent of simple offset or gain shifts. Step-by-Step Solution: Define ideal relationship: V_out,ideal = slope * code + intercept.Measure actual V_out at each code.Compute error to the reference straight line; the maximum magnitude is the linearity error (often in LSBs).Therefore linearity corresponds to deviation from a straight line, not step count, accuracy comparison, or direction resolution. Verification / Alternative check: Data sheets specify INL in LSB; a low INL value means the transfer closely follows a straight line across codes. Why Other Options Are Wrong: Reciprocal of steps: That is resolution (1/2^N of full scale). Comparison actual vs expected: That is overall accuracy (includes offset, gain, linearity). Ability to resolve forward vs reverse steps: That describes monotonicity/hysteresis behavior, not linearity. Common Pitfalls: Equating precision (repeatability) with accuracy or linearity. Assuming high resolution guarantees good linearity—these are independent. Final Answer: It is the deviation between the ideal straight-line output and the actual output of the converter.

Question 12

Offset error in DAC transfer characteristics Which description best matches offset error for a digital-to-analog converter (DAC)?

Accepted Answer

Introduction / Context: Static DAC errors are commonly categorized as offset error, gain (full-scale) error, differential nonlinearity (DNL), and integral nonlinearity (INL). Correctly identifying these helps diagnose performance issues and interpret data sheets. Given Data / Assumptions: Zero-code and first-transition behavior indicate offset. Overall slope indicates gain error. Step uniformity indicates DNL; cumulative deviation indicates INL. Concept / Approach: Offset error shifts the entire transfer function by a constant amount. Practically, the first code transition occurs at a non-ideal level (too low or too high). In staircase terms, the whole staircase is displaced up or down without changing its slope. Step-by-Step Solution: Consider the ideal first transition at one-half LSB (for a mid-tread DAC) or at 0 V (for specific coding).If the measured first transition occurs earlier or later, a constant offset exists.This matches the description that “more or less input voltage is required for the first step than specified,” i.e., the step threshold is shifted.Therefore option (c) describes offset error most directly. Verification / Alternative check: Graphically, offset error is the vertical intercept difference between actual and ideal straight lines; once compensated, subsequent steps align (ignoring other errors). Why Other Options Are Wrong: missing codes: A DNL issue where certain codes never appear. error in the slope: That is gain (full-scale) error, not offset. —: Not a technical description. Common Pitfalls: Confusing offset with gain; offset shifts all codes equally, gain tilts the line. Assuming offset affects linearity; it does not, by definition. Final Answer: more or less input voltage is required for the first step than what is specified

Question 13

Analog vs. digital descriptions — what defines an analog quantity? Which statement correctly characterizes an analog quantity in measurement and signal processing?

Accepted Answer

Introduction / Context: In electronics, we model information either as analog (continuous-value) or digital (discrete-level). Recognizing the difference is foundational for choosing sensors, converters, and processing techniques. Given Data / Assumptions: Analog quantities can take any value within limits, not just predefined steps. Digital quantities are quantized into discrete levels (bits or codes). Concept / Approach: An analog signal varies continuously with time or some independent variable. The key defining attribute is continuity of value within a range, independent of whether the dependence is linear, logarithmic, or arbitrary. Step-by-Step Solution: Identify options that imply discreteness (steps, quantization) → these are digital traits.Option (d) states continuity of values—this matches the analog definition.Therefore, select option (d). Verification / Alternative check: Examples: microphone voltage vs. sound pressure, thermocouple voltage vs. temperature—both produce continuous outputs until digitized by an ADC. Why Other Options Are Wrong: Discrete levels/finite steps: digital, not analog. Logarithmic curve: Possible for an analog sensor, but not a defining property. Common Pitfalls: Confusing the shape of a transfer function (e.g., logarithmic) with the continuous nature of analog values. Assuming continuous time implies analog values; sampling affects time but not necessarily value quantization. Final Answer: It has a continuous set of values over a given range.

Question 14

Relative complexity and speed: A/D versus D/A conversion When comparing digital-to-analog (D/A) and analog-to-digital (A/D) conversion processes in general-purpose systems, which statement is typically true?

Accepted Answer

Introduction / Context: D/A and A/D conversions bridge the analog and digital worlds. DACs reconstruct an analog level from a code, whereas ADCs must decide the correct code from an analog input. The direction of conversion strongly affects design complexity and time behavior. Given Data / Assumptions: We compare common, mainstream architectures (e.g., R-2R DACs; SAR, sigma-delta, flash ADCs). We consider typical resolution ranges (8–16 bits) and moderate speeds. Concept / Approach: DACs generate an output by summing weighted elements; the operation is instantaneous aside from settling time. ADCs must measure and decide between many possible codes, requiring successive approximation, oversampling/noise-shaping, or many comparators; these processes take more time and control logic, making A/D generally more complex and slower for a given technology and accuracy. Step-by-Step Solution: Recognize that ADCs perform a search or average to determine the correct code.These actions consume clock cycles (SAR) or long integration/decimation (sigma-delta) or large hardware (flash).DACs primarily settle to a value; no code search is required.Therefore, A/D is typically more complicated and more time consuming than D/A. Verification / Alternative check: Compare datasheets: for comparable resolution, DACs often achieve faster update rates than ADCs achieve sampling rates, barring specialized architectures. Why Other Options Are Wrong: Less complicated/time consuming: Contradicts the need for decision processes in A/D. More complicated but less time consuming: Rarely true outside of niche, very-high-speed flash vs. slow DACs. Common Pitfalls: Assuming “fast ADCs exist, so A/D is always faster”—context matters; for mainstream use, A/D tends to be the bottleneck. Final Answer: more complicated and more time consuming than the D/A conversion.

Question 15

Simultaneous (flash) A/D converters — identify the main drawback In a simultaneous, or flash, analog-to-digital converter, what is the primary disadvantage when targeting reasonable resolutions?

Accepted Answer

Introduction / Context: Flash ADCs achieve extreme speed by comparing the input against many reference thresholds in parallel. While this gives near-instant conversions, it incurs a steep hardware cost that grows exponentially with resolution. Given Data / Assumptions: N-bit flash ADC uses 2^N − 1 comparators and a thermometer-to-binary encoder. Each additional bit doubles the number of comparators. Concept / Approach: The key drawback is scaling: for N = 8 bits, 255 comparators are required; for 10 bits, 1023 comparators. This increases die area, power, input capacitance, and matching challenges, making higher resolutions impractical without time-interleaving or alternative architectures. Step-by-Step Solution: Identify flash architecture's advantage: conversion speed.Identify the cost: comparator count = 2^N − 1.Associate impacts: power, heat, area, and calibration complexity.Hence, the main disadvantage is the large number of comparators required. Verification / Alternative check: Industry practice uses flash for low resolution at very high speed or employs pipeline/SAR/sigma-delta for higher resolutions, precisely to avoid comparator explosion. Why Other Options Are Wrong: Requiring the input voltage simultaneously: The input is common; this is not a drawback. Long conversion time: Flash is the fastest ADC type. Large number of output lines: Thermometer encoding is handled internally; external binary outputs scale reasonably. Common Pitfalls: Assuming comparator count is linear with resolution—it's exponential. Final Answer: the large number of comparators required to represent a reasonable sized binary number

Question 16

Tracking (up/down) digital-ramp ADC In practical data-converter design, how would you characterize the conversion speed of an up/down tracking (digital-ramp) ADC compared with other common architectures such as SAR or flash?

Accepted Answer

Introduction / Context: The up/down tracking (digital-ramp) ADC is a classic converter architecture used when simplicity and low cost are more important than raw speed. Unlike flash or successive-approximation (SAR) converters, the tracking ADC adjusts its internal count step by step toward the input value, which has direct consequences for speed and response time. Given Data / Assumptions: The device is a tracking (up/down) digital-ramp ADC. We are comparing its speed qualitatively against other architectures. No specific clock or resolution is provided; focus is on architectural behavior. Concept / Approach: A tracking ADC uses a counter and a DAC. The comparator determines if the DAC's output is above or below the analog input, then the counter increments or decrements by one step per clock until it matches the input. This “chasing” behavior means conversion time depends on how far the current code is from the new code, which can be many counts for large signal changes. Step-by-Step Solution: Tracking action: one code step per clock tick toward the input.Large input changes → many steps → many clock cycles → longer conversion time.Compare to SAR: binary search in roughly n steps regardless of input → much faster and deterministic.Compare to flash: parallel comparators resolve in one comparator delay → fastest. Verification / Alternative check: Datasheet comparisons typically show tracking ADCs with bandwidth limited by the counter step rate; SAR devices at the same resolution complete conversions in a fixed, small number of cycles (for example, 8–16 cycles), confirming tracking ADCs are slower overall. Why Other Options Are Wrong: 20 µs / 10 µs / 1 µs: These are arbitrary numbers and depend on clock, resolution, and design. The correct characterization is architectural, not a fixed time. Common Pitfalls: Assuming speed is constant; tracking ADC time varies with input step size. Confusing tracking with SAR, which does not step linearly code by code. Final Answer: Relatively slow

Question 17

Electrical quantities can be interpreted without conditioning by a digital computer.

Accepted Answer

False

Question 18

An AD7524 is an eight-bit D/A converter that uses an R/2R ladder network.

Accepted Answer

True

Question 19

Two characteristics of ideal operational amplifiers are very high input impedance and very high voltage gain.

Accepted Answer

True

Question 20

The output voltage or current of a digital-to-analog converter is truly an analog signal.

Accepted Answer

False

Interfacing to the Analog World Questions