Gated D flip-flop (level-enabled) — correct behavior Which statement correctly describes a gated (enable-controlled) D flip-flop or D latch when the enable input is asserted?

Introduction / Context:
Gated D devices (often called D latches when level-controlled) are transparent while enabled and hold data when disabled. Being able to state their behavior succinctly is essential when building registers, FIFOs, or two-phase latch pipelines.

Given Data / Assumptions:

• There is a data input D, an enable input (EN), and outputs Q and possibly Q'.
• Enable is active-HIGH.
• We are focusing on functional behavior, not electrical details.

Concept / Approach:
When EN is HIGH, the internal gating opens, allowing D to propagate to Q (subject to propagation delay). When EN goes LOW, the path is blocked and Q retains the last value sampled just before disabling. This is the hallmark of a level-sensitive D storage element.

Step-by-Step Solution:

Verification / Alternative check:
Timing diagrams show Q changing only during intervals where EN is asserted; otherwise it remains constant despite D activity.

Why Other Options Are Wrong:

• Toggling with one input HIGH (a) and mutual exclusion of inputs (b) describe JK behavior, not D devices.
• Output complement follows input (c) is incorrect; Q follows D, not Q'.

Common Pitfalls:
Confusing a gated D latch with an edge-triggered D flip-flop, which updates only at a clock edge rather than during the entire enable interval.

Final Answer:
Q output follows the input D when the enable is HIGH.