S–R flip-flop limitation — identifying the classic disadvantage What is one widely recognized disadvantage of an S–R (Set–Reset) flip-flop implementation?

Introduction / Context:
The basic S–R flip-flop (or latch) is instructive but has a well-known drawback. Recognizing this limitation guides designers toward D or JK flip-flops when deterministic behavior is required, especially in synchronous systems where simultaneous assertion of set and reset must be handled predictably.

Given Data / Assumptions:

• S–R built from cross-coupled NOR (active-HIGH) or NAND (active-LOW) gates.
• Two outputs: Q and Q' intended to be complementary.
• We evaluate functional limitations, not specific vendor implementations.

Concept / Approach:
With a NOR-based S–R latch, the input combination S=1 and R=1 drives both outputs LOW, violating complementarity and creating an invalid/forbidden state. Similarly, for NAND-based active-LOW inputs, S=0 and R=0 is forbidden. The aftermath when the inputs return to the idle state can be unpredictable and dependent on device delays, which undermines reliable operation.

Step-by-Step Solution:

Verification / Alternative check:
Simulate with a gate-level model: apply the forbidden combination and then release simultaneously—final Q may depend on slight delay differences, confirming the hazard.

Why Other Options Are Wrong:

• No enable input: not inherent; enables can be added externally.
• No clock input: true for a latch, but clocked S–R flip-flops exist.
• Single output: incorrect; Q and Q' are both available.

Common Pitfalls:
Forgetting which input polarity is active for NOR vs. NAND versions when identifying the forbidden combination.

Final Answer:
It has an invalid state.