Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Flip-Flops
If an input is activated by a signal transition, it is ________.
edge-triggered
toggle triggered
clock triggered
noise triggered
Correct Answer:
edge-triggered
← Previous Question
Next Question→
More Questions from
Flip-Flops
Which of the following is correct for a gated D flip-flop?
What is one disadvantage of an S-R flip-flop?
A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
The output of a gated S-R flip-flop changes only if the:
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
Which is not an Altera primitive port identifier?
Connecting components together using HDL is not difficult.
VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.
A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments