Difficulty: Easy
Correct Answer: sample-and-hold circuit
Explanation:
Introduction / Context: During an A/D conversion, many architectures require a stable input over the conversion interval. If the source is moving (sensor drift, mains ripple, or multiplexed channels), the ADC may sample inconsistent values across its internal phases unless the signal is briefly “frozen.”Given Data / Assumptions:
Concept / Approach: A sample-and-hold (S/H) circuit samples the input onto a capacitor through a switch, then opens the switch, isolating the capacitor to hold the voltage while the ADC processes. A buffer amplifier with low leakage minimizes droop, preserving accuracy throughout conversion.Step-by-Step Solution:
Place S/H before ADC input.On sample command, close the switch to charge the hold capacitor to the input voltage.Open the switch to hold the voltage constant while the ADC converts.Verification / Alternative check:
Datasheets of SAR ADCs specify acquisition and hold times; S/H meets these requirements.Why Other Options Are Wrong:
op-amp comparator: Compares two voltages; does not hold a level.NPN amp: A generic amplifier stage without hold functionality.current loop: Refers to a transmission scheme, not voltage holding.Common Pitfalls:
Using too small a hold capacitor, causing excessive droop.Ignoring source impedance and switch on-resistance during acquisition.Final Answer:
sample-and-hold circuit
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