Clock usage — Which ADC architecture does not require a clock because it performs no sequential timing or bit-by-bit decision process?

Introduction / Context:
Many ADCs rely on timing sequences (e.g., SAR bit trials, integrating cycles), which require clock signals. However, one architecture works by making all comparisons in parallel with no sequential steps, and thus no conversion clock is strictly required for its core decision.

Given Data / Assumptions:

• We focus on the core conversion mechanism, not on digital interface housekeeping.
• Parallel comparison against multiple thresholds is used.
• An encoder converts thermometer code to binary.

Concept / Approach:
A flash ADC employs a bank of comparators referencing a resistor ladder. The output is determined as soon as comparator outputs settle; no iterative clocked sequence is needed. While practical systems may still clock the readout or pipeline stages, the essential conversion itself is asynchronous.

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