Fixed conversion-time ADCs: Which ADC architecture has a fixed conversion time that does not depend on the magnitude of the analog input value?

Introduction / Context:
ADC conversion time impacts sampling rate and latency. Some architectures take longer when the input is near one extreme; others complete in a constant number of steps regardless of the input code. Identifying which is which is crucial for real-time designs.

Given Data / Assumptions:

• We compare common ADC types: dual-slope, counter-ramp, successive-approximation (SAR).
• “Fixed conversion time” means a predictable, constant number of cycles per sample.
• Input amplitude should not change the duration.

Concept / Approach:
A SAR ADC performs a binary search through all bit positions in exactly N steps for an N-bit result. The process sets MSB..LSB decisions in sequence using an internal DAC and comparator; thus conversion time is deterministic. Counter-ramp time depends on the final code (must count from zero to the target), and dual-slope includes a fixed integrate phase but a de-integrate phase that varies with input, so total time is not strictly constant with amplitude.

Step-by-Step Solution:

Verification / Alternative check:
Datasheets specify “conversion time = N * t_clk” for SAR, versus “max conversion time up to full-scale” for ramp types and “measurement time set by integration window” for dual-slope with variable back-half.

Why Other Options Are Wrong:

• Substandard/Recessive-approximation: Not standard ADC categories.
• Dual: Not fixed total time vs input; accuracy advantage lies elsewhere (noise rejection).

Common Pitfalls:
Confusing “sampling rate” with “throughput”; assuming dual-slope is fixed because its first phase is fixed—overall time still depends on input during de-integration.

Final Answer:
Successive-approximation