Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Take Free Test
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Take Free Test
Home
»
Digital Electronics
»
Flip-Flops
The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.
point 4
points 3 and 4
points 1 and 2
points 4 and 5
Correct Answer:
point 4
← Previous Question
Next Question→
More Questions from
Flip-Flops
A gated S-R flip-flop goes into the CLEAR condition when ________.
The signal used to identify edge-triggered flip-flops is ________.
A gated D latch does not have ________.
A positive edge-triggered flip-flop will accept inputs only when the clock ________.
A gated S-R flip-flop is in the hold condition whenever ________.
The postponed symbol () on the output of a flip-flop identifies it as being ________.
When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.
The advantage of a J-K flip-flop over an S-R FF is that ________.
A major drawback to an latch is its ________.
The action of ________ a FF or latch is also called resetting.
Discussion & Comments
No comments yet. Be the first to comment!
Name
Comment
Post Comment
Join Discussion
Discussion & Comments