SRAM vs. DRAM – key operational difference What is the major difference between Static RAM (SRAM) and Dynamic RAM (DRAM) in normal operation?

Introduction / Context:SRAM and DRAM are the two dominant volatile memory technologies. Designers must know how their internal storage mechanisms impact system timing and controller complexity.

Given Data / Assumptions:

• SRAM uses cross-coupled latches (typically 6-transistor cells).
• DRAM uses capacitors to store charge in 1-transistor cells.
• Both lose data when power is removed (volatile).

Concept / Approach:DRAM cell charge leaks, so each row must be refreshed (read and rewritten) within the specified interval. SRAM stores data as a stable latch state and does not require refresh while powered, simplifying timing at the cost of lower density per bit.

Step-by-Step Solution:Identify storage mechanism: charge (DRAM) vs. latch (SRAM).Derive operational requirement: DRAM needs periodic refresh; SRAM does not.Conclude the major difference is the refresh requirement in DRAM.

Verification / Alternative check:Memory controller specs include refresh cycles for DRAM. SRAM timing diagrams lack refresh signals and can support random access without periodic maintenance.

Why Other Options Are Wrong:SRAM does not retain data without power; both are volatile.Drain/Source terminal choice is not the defining distinction.DRAMs are not “always active,” and SRAMs do not require resets between accesses.

Common Pitfalls:Confusing nonvolatile memories (EEPROM/flash) with SRAM; believing DRAM reads are inherently destructive without rewrite (modern DRAM controllers automatically perform the necessary restore after reads).

Final Answer:DRAMs must be periodically refreshed.