Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Take Free Test
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Take Free Test
Home
»
Digital Electronics
»
Flip-Flops
The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
True
False
Correct Answer:
False
← Previous Question
Next Question→
More Questions from
Flip-Flops
The S-R flip-flop has no invalid or unused state.
A one-shot circuit is also known as a timer.
Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.
When the output of the NOR gate S-R flip-flop is and , the inputs are .
Some flip-flops have invalid states.
A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.
ICs can perform sequential operations, including counting and data shifting.
It takes four flip-flops to act as a divide-by-4 frequency divider.
An astable multivibrator is sometimes referred to as a clock.
Discussion & Comments
No comments yet. Be the first to comment!
Name
Comment
Post Comment
Join Discussion
Discussion & Comments