Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Flip-Flops
A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.
True
Correct Answer:
False
← Previous Question
Next Question→
More Questions from
Flip-Flops
A flip-flop is in the CLEAR condition when .
The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
A D latch has one data-input line.
The 7474 has two distinct types of inputs: synchronous and asynchronous.
The gated S-R flip-flop is asynchronous.
Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.
A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.
Multivibrators must be level-triggered.
Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.
The 555 timer can be used in either the astable or monostable modes.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments