Counters Questions

• The terminal count of a typical modulus-10 binary counter is ________.
• What is the difference between combinational logic and sequential logic?
• The parallel outputs of a counter circuit represent the:
• Which of the following statements are true?
• Which is not an example of a truncated modulus?
• What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
• How many different states does a 3-bit asynchronous counter have?
• MOD-6 and MOD-12 counters and multiples are most commonly used as:
• Once an up-/down-counter begins its count sequence, it cannot be reversed.
• A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
• A principle regarding most display decoders is that when the correct input is present, the related output will switch:
• Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
• What function will the counter shown below be performing during period "B" on the timing diagram?
• Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.
• The terminal count of a modulus-11 binary counter is ________.
• Which of the following is an example of a counter with a truncated modulus?
• Which of the following procedures could be used to check the parallel loading feature of a counter?
• Referring to the given figure, what causes the Control FF to reset after D7?
• The circuit given below has no output on Q1 when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?
• Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?